View DJIXFECD0SE000_4811989.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

intel ? lxt9785 and intel ? lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet the intel ? lxt9785 and intel ? lxt9785e are 8-port fast ethernet phy transceivers supporting ieee 802.3 physical layer applicati ons at 10 mbps and 100 mbps. these devices provide serial/source synchrono us serial media independent interfaces (smii/ ss-smii) and reduced media independent in terface (rmii) for switching and other independent port applications. the lxt9785 and lxt9785e are id entical except for the ip telephony features included in the lxt9785e transceiver. the lxt9785e is an enhanced version of the lxt9785 that detects data terminal equipment (dte) requiring power from the switch over a cat5 cable. the system uses the information collected by the lxt97985e to apply power if the dte at the far end requires power over the cable, such as an ip telephone. each network port can provide a twisted-pair (tp) or low-voltage positive emitter coupled logic (lvpecl) interface. the twisted-pa ir interface supports 10 mbps and 100 mbps (10base-t and 100base-tx) et hernet over twisted-pair. the lvpecl interface supports 100 mbps (100base-fx) ethernet over fiber-optic media. the lxt9785/lxt9785e provides three discrete led driver out puts for each port. the devices support both half-duplex and full-duplex operation at 10 mbps and 100 mbps and require only a single 2.5 v power supply. applications product features ? enterprise switches ? ip telephony switches ? storage area networks ? multi-port network in terface cards (nics) ? eight ieee 802.3-compliant 10base-t or 100base-tx ports with integrated filters. ? 100base-fx fiber-optic capability on all ports. ? 2.5 v operation. ? low power consumption; 250 mw per port typical. ? multiple rmii or smii/ss-smii ports for independent phy port operation. ? auto mdi/mdix crossover capability. ? proprietary optimal signal processing? architecture improves snr by 3 db over ideal analog filters. ? optimized for dual-h igh stacked rj-45 applications. ? mdio sectionalization into 2x4 or 1x8 configurations. ? supports both auto-negotiation systems and legacy systems without auto-negotiation capability. ? robust baseline wander correction. ? configurable through the mdio port or external control pins. ? jtag boundary scan. ? 208-pin pqfp: lxt9785hc, lxt9785ehc, lxt9785he. ? 241-ball bga: lxt9785bc, lxt9785ebc. ? 196-ball bga: lxt9785mbc ? dte detection for remote powering applications (lxt9785e only). ? extended temperatur e operation of -40 o c to +85 o c (lxt9785he). document number: 249241 revision number: 007 revision date: august 28, 2003
2 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property righ ts is granted by this document. except as provided in intel's terms and conditions of sale for such products, in tel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products includi ng liability or warranties relating to fitness for a particular purpose, merchantabili ty, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, life sustaining applications. intel may make changes to specifications and pr oduct descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instruct ions marked ?reserved? or ?undefined.? int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the intel ? lxt9785 and intel ? lxt9785e may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characte rized errata are available on request. contact your local intel sales office or your distributor to obt ain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are refer enced in this document, or other intel literature may be obtaine d by calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com. anypoint, appchoice, boardwatch, bunnypeople, cableport, celeron, chips, ct media, dialogic, dm3, etherexpress, etox, flashfile , i386, i486, i960, icomp, instantip, intel, intel centrino, intel logo, intel386, intel486, intel740, inteldx2, inteldx4, intelsx2, intel cr eate & share, intel gigablade, intel inbusiness, intel inside, intel inside logo, intel netburst, intel netmerge, intel netstructure, intel play, intel play l ogo, intel singledriver, intel speedstep, intel strataflash, intel teamstation, intel xeon, intel xscale, iplink, itanium, mcs, mmx, mmx logo, optimizer logo, overdrive, paragon, pc dads, pc parents, pdcharm, pentium, pentium ii xe on, pentium iii xeon, performance at your command, remoteexpress, smartdie, solutions960, sound mark, storageexpress, the computer inside., the journey inside, tokenexpress , voicebrick, vtune, and xircom are trademarks or registered trademarks of intel corporation or it s subsidiaries in the united states and other countries. *other names and brands may be claimed as the property of others. copyright ? 2003, intel corporation
datasheet 3 document number: 249241 revision number: 007 revision date: august 28, 2003 contents contents 1.0 introduction ............................................................................................................................... ... 18 1.1 what you will find in this document ......... ....................................................................... 18 1.2 related documents ........................................................................................................... .18 2.0 block diagram ............................................................................................................................. 19 3.0 pin/ball assignments and signal descriptions ........................................................................ 20 3.1 pqfp pin assignments ...................................................................................................... 20 3.1.1 pqfp pin assignments ? rmii configuration ....................................................... 21 3.1.2 pqfp pin assignments ? smii configuration........................................................ 26 3.1.3 pqfp pin assignments ? ss-smii configuration.................................................. 31 3.2 pqfp signal descriptions .............................. .................................................................... 36 3.2.1 signal name conventions ..................... ................................................................ 36 3.2.2 pqfp signal description s ? rmii, smii, and ss-smii co nfigurations.................. 36 3.3 bga23 ball assignments.................................................................................................... 51 3.3.1 rmii bga23 ball list ............................................................................................. 52 3.3.2 smii bga23 ball list ............................................................................................. 62 3.3.3 ss-smii bga23 ball list ....................................................................................... 72 3.4 bga23 signal descriptions ................................................................................................ 82 3.4.1 signal name conventions ..................... ................................................................ 82 3.4.2 signal descriptions ? rmii, smii, and ss-smii config urations............................. 82 3.5 bga15 ball assignments.................................................................................................... 98 3.5.1 bga15 ball list...................................................................................................... 99 3.6 bga15 signal descriptions ..............................................................................................109 3.6.1 signal name conventions ..................... ..............................................................109 3.6.2 signal descriptions ? smii and ss-smii configuratio ns .....................................109 4.0 functional description ..............................................................................................................116 4.1 introduction ................................................................................................................ .......116 4.1.1 osp? architecture .............................................................................................116 4.1.2 comprehensive functiona lity ..............................................................................117 4.1.2.1 sectionalization ....................................................................................117 4.2 interface descriptions ...................................................................................................... .117 4.2.1 10/100 network interface.....................................................................................117 4.2.1.1 twisted-pair interface ..........................................................................118 4.2.1.2 mdi crossover (mdix).........................................................................119 4.2.1.3 fiber interface......................................................................................119 4.3 media independent interface (mii) interfaces...................................................................119 4.3.1 global mii mode select .......................................................................................119 4.3.2 internal loopback ................................................................................................120 4.3.3 rmii data interface..............................................................................................120 4.3.4 serial media independent interf ace (smii) and source synchronous- serial media independent interface (ss-smii) ....................................................121 4.3.4.1 smii interface.......................................................................................121 4.3.4.2 source synchronous-serial medi a independent interface ..................121 4.3.5 configuration management interface ..................................................................121 4.3.6 mii isolate ............................................................................................................121
contents 4 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 4.3.7 mdio management interface .............................................................................. 121 4.3.8 mii sectionalization.............................................................................................. 123 4.3.9 mii interrupts........................................................................................................ 123 4.3.10 global hardware control interface ...................................................................... 124 4.3.11 fifo initial fill values.......................................................................................... 124 4.4 operating requirements................................................................................................... 125 4.4.1 power requirements ...... ..................................................................................... 125 4.4.2 clock/sync requirements ................................................................................. 125 4.4.2.1 reference clock .................................................................................. 125 4.4.2.2 txclk signal (ss-smii only)............................................................... 125 4.4.2.3 txsync signal (smii/ss-smii)........................................................... 125 4.4.2.4 rxsync signal (ss-smii only) ... ........................................................ 125 4.4.2.5 rxclk signal (ss-smii only) .............................................................. 126 4.5 initialization .............................................................................................................. ......... 126 4.5.1 mdio control mode............................................................................................. 126 4.5.2 hardware control mode....................................................................................... 126 4.5.3 power-down mode .............................................................................................. 127 4.5.3.1 global (hardware) power down .......................................................... 128 4.5.3.2 port (software) power down ............................................................... 128 4.5.4 reset ................................................................................................................... 12 8 4.5.5 hardware configuration settings......................................................................... 129 4.6 link establishment.......................................................................................................... .. 129 4.6.1 auto-negotiation .................................................................................................. 129 4.6.1.1 base page exchange .......................................................................... 129 4.6.1.2 manual next page exchange .............................................................. 130 4.6.1.3 controlling auto-negotiation ................................................................ 130 4.6.1.4 link criteria.......................................................................................... 130 4.6.1.5 parallel detection................................................................................. 131 4.6.1.6 reliable link establishm ent while auto mdi/mdix is enabled in forced speed mode .......................................................... 131 4.7 serial mii operation........................................................................................................ .. 132 4.7.1 smii reference clock.......................................................................................... 135 4.7.2 txsync pulse (smii/ss-smii)............................................................................ 135 4.7.3 transmit data stream.......................................................................................... 135 4.7.3.1 transmit enable................................................................................... 135 4.7.3.2 transmit error ...................................................................................... 135 4.7.4 receive data stream........................................................................................... 136 4.7.4.1 carrier sense....................................................................................... 136 4.7.4.2 receive data valid .............................................................................. 136 4.7.4.3 receive error ....................................................................................... 136 4.7.4.4 receive status encoding..................................................................... 136 4.7.5 collision ............................................................................................................... 13 6 4.7.6 source synchronous-serial media inde pendent interface .................................. 137 4.8 rmii operation .............................................................................................................. ... 141 4.8.1 rmii reference clock.......................................................................................... 141 4.8.2 transmit enable................................................................................................... 142 4.8.3 carrier sense & data valid.................................................................................. 142 4.8.4 receive error....................................................................................................... 142 4.8.5 out-of-band signaling ......................................................................................... 142 4.8.6 4b/5b coding operations .................................................................................... 142 4.9 100 mbps operation ......................................................................................................... 1 45
datasheet 5 document number: 249241 revision number: 007 revision date: august 28, 2003 contents 4.9.1 100base-x network operations .............. ................ ................ ................ ...........145 4.9.2 100base-x protocol sublay er operations..... ................ ................. ............ ........145 4.9.2.1 pcs sublayer ......................................................................................145 4.9.3 pma sublayer ......................................................................................................147 4.9.3.1 link ......................................................................................................148 4.9.3.2 link failure override............................................................................148 4.9.3.3 carrier sense/data valid (rmii) ..........................................................148 4.9.3.4 carrier sense (smii) ............................................................................148 4.9.3.5 receive data valid (smii)......... ...........................................................148 4.9.3.6 twisted-pair pmd sublayer .................................................................149 4.9.3.7 fiber pmd sublayer.............................................................................149 4.10 10 mbps operation .......................................................................................................... .150 4.10.1 preamble handling ..............................................................................................150 4.10.2 dribble bits ..........................................................................................................151 4.10.3 link test ..............................................................................................................15 1 4.10.3.1 link failure ..........................................................................................151 4.10.4 jabber ..................................................................................................................1 51 4.11 dte discovery process ....................................................................................................15 2 4.11.1 definitions ............................................................................................................15 2 4.11.2 interaction between processor, mac, and phy ..................................................153 4.11.3 management interface and control .....................................................................153 4.11.4 dte discovery process flow ................ ..............................................................154 4.11.5 dte discovery behavior. .....................................................................................155 4.12 monitoring operations ...................................................................................................... 157 4.12.1 monitoring auto-negotiation .............. ..................................................................157 4.12.2 per-port led driver functions .......... ..................................................................157 4.12.3 out-of-band signaling .... .....................................................................................158 4.12.4 boundary scan interface .....................................................................................159 4.12.5 state machine ......................................................................................................159 4.12.6 instruction register ............................ ..................................................................159 4.12.7 boundary scan register .................... ..................................................................159 4.13 cable diagnostics overview .............................................................................................160 4.13.1 features...............................................................................................................16 0 4.13.2 operation .............................................................................................................160 4.13.2.1 short and long cable testing requirements ......................................160 4.13.2.2 precision ..............................................................................................160 4.13.3 implementation considerations ............. ..............................................................161 4.13.4 basic implementation ..... .....................................................................................161 4.14 link hold-off overview ..................................................................................................... 162 4.14.1 features...............................................................................................................16 2 4.14.2 operation .............................................................................................................163 5.0 application information ............................................................................................................164 5.1 design recommendations................................................................................................164 5.2 general design guidelines ...............................................................................................164 5.2.1 power supply filtering ....................... ..................................................................164 5.2.2 power and ground plane layout considerations................................................165 5.2.2.1 chassis ground ...................................................................................165 5.2.3 mii terminations ..................................................................................................165 5.2.4 twisted-pair interface ..........................................................................................165 5.2.4.1 magnetic requirements .......................................................................166
contents 6 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 5.2.5 the fiber interface .............................................................................................. 166 5.2.6 led circuit........................................................................................................... 167 5.3 typical application circuits............................................................................................... 1 68 6.0 test specifications .................................................................................................................... 173 7.0 register definitions ................................................................................................................... 199 8.0 package specifications ............................................................................................................. 221 9.0 ordering information ................................................................................................................. 227 figures 1 intel ? lxt9785/lxt9785e block diagram ................................................................................. 19 2 intel ? lxt9785 and intel ? lxt9785e rmii 208-pin pqfp assignments .................................. 21 3 intel ? lxt9785/lxt9785e smii 208-pin pqfp assignments ................................................... 26 4 intel ? lxt9785/lxt9785e ss-smii 208-pin pqfp assignments ............................................. 31 5 intel? lxt9785/lxt9785e 241-ball bga23 assignments (top view)...................................... 51 6 intel ? lxt9785mbc 196-ball bga15 assignments (top view) ................................................ 98 7 intel ? lxt9785/lxt9785e interfaces ...................................................................................... 118 8 intel ? lxt9785/lxt9785e internal loopback........... ............................................................... 120 9 intel ? lxt9785/lxt9785e management interface read frame structure.............................. 122 10 intel ? lxt9785/lxt9785e management interface write frame structure .............................. 122 11 intel ? lxt9785/lxt9785e port address scheme ................................................................... 123 12 intel ? lxt9785/lxt9785e interrupt logic ................ ............................................................... 124 13 intel ? lxt9785/lxt9785e initialization sequence .................................................................. 127 14 intel ? lxt9785/lxt9785e auto -negotiation operation........................................................... 131 15 intel ? lxt9785/lxt9785e typical smii interface diagram ..................................................... 133 16 intel ? lxt9785/lxt9785e typical smii quad sect ionalization diagram ................................ 134 17 intel ? lxt9785/lxt9785e 100 mbps serial mii data flow ..................................................... 135 18 intel ? lxt9785/lxt9785e serial mii transmit sy nchronization ............................................. 136 19 intel ? lxt9785/lxt9785e serial mii receive synchronization .............................................. 137 20 intel ? lxt9785/lxt9785e typical ss-smii interfac e diagram ............................................... 139 21 intel ? lxt9785/lxt9785e typical ss-smii quad se ctionalization diagram .......................... 140 22 intel ? lxt9785/lxt9785e ss-smii transmit timing .............................................................. 141 23 intel ? lxt9785/lxt9785e ss-smii receive timing ............................................................... 141 24 intel ? lxt9785/lxt9785e rmii data flow ............................................................................. 142 25 intel ? lxt9785/lxt9785e typical rmii interface diagram..................................................... 143 26 intel ? lxt9785/lxt9785e typical rmii quad sectionalization diagram................................ 144 27 intel ? lxt9785/lxt9785e 1 00base-x frame format ... ................ ................ ................ ........ 145 28 intel ? lxt9785/lxt9785e protocol sublayers ........................................................................ 146 29 typical ip telephone system connection................................................................................ 152 30 intel ? lxt9785e negotiation flow chart ................................................................................. 156 31 intel ? lxt9785/lxt9785e led pulse stretching .................................................................... 158 32 intel ? lxt9785/lxt9785e rmii programmable out-of-band signaling.................................. 158 33 led circuit .................................................................................................................. ............. 167 34 intel ? lxt9785/lxt9785e powe r and ground supply connections ....................................... 168 35 intel ? lxt9785/lxt9785e typical twisted-pair interface ....................................................... 169 36 recommended intel ? lxt9785/lxt9785e -to-3.3 v fiber tr ansceiver interface circuitry ...... 170 37 recommended intel ? lxt9785/lxt9785e -to-5 v fiber transceiver in terface circuitry ......... 171 38 on semiconductor triple pecl-to-lvpecl transla tor ............ ............ ............. ............. ........ 172
datasheet 7 document number: 249241 revision number: 007 revision date: august 28, 2003 contents 39 intel ? lxt9785/lxt9785e smii - 100base-tx receiv e timing........ ................. ............ ........178 40 intel ? lxt9785/lxt9785e smii - 100base-tx transm it timing................. ................ ...........179 41 intel ? lxt9785/lxt9785e smii - 100base-fx receiv e timing........ ................. ............ ........180 42 intel ? lxt9785/lxt9785e smii - 100base-fx transm it timing................. ................ ...........181 43 intel ? lxt9785/lxt9785e smii - 10base-t receive timing ............ ................. ............ ........182 44 intel ? lxt9785/lxt9785e smii - 10 base-t transmit timing ........... ................. ............ ........183 45 intel ? lxt9785/lxt9785e ss-smii - 100base-tx receive timing.......................................184 46 intel ? lxt9785/lxt9785e ss-smii - 100base-tx tran smit timing......................................185 47 intel ? lxt9785/lxt9785e ss-smii - 100base-fx receive timing.......................................186 48 intel ? lxt9785/lxt9785e ss-smii - 100base-fx tran smit timing......................................187 49 intel ? lxt9785/lxt9785e ss-smii - 10base-t receive timing .......... ............. ............ ........188 50 intel ? lxt9785/lxt9785e ss-smii - 10base-t transmit timing .................. ................ ........189 51 intel ? lxt9785/lxt9785e rmii - 100base-tx receiv e timing ....... ................. ............ ........190 52 intel ? lxt9785/lxt9785e rmii - 1 00base-tx transmit timing ...... ................. ............ ........191 53 intel ? lxt9785/lxt9785e rmii - 100base-fx receiv e timing ....... ................. ............ ........192 54 intel ? lxt9785/lxt9785e rmii - 1 00base-fx transmit timing ...... ................. ............ ........193 55 intel ? lxt9785/lxt9785e rmii - 10base-t receive timing............ ................. ............ ........194 56 intel ? lxt9785/lxt9785e rmii - 10 base-t transmit timing........... ................. ............ ........195 57 intel ? lxt9785/lxt9785e auto-negotiation and fast link pulse timing ...............................196 58 intel ? lxt9785/lxt9785e fast link pulse timing ..................................................................196 59 intel ? lxt9785/lxt9785e mdio write timing (mdio sourced by mac)...............................197 60 intel ? lxt9785/lxt9785e mdio read timing (mdio sourced by phy) ...............................197 61 intel ? lxt9785/lxt9785e power-up timing............. ..............................................................198 62 intel ? lxt9785/lxt9785e reset recovery timing .................................................................198 63 phy identifier bit mapping................................................................................................... .....203 64 intel ? lxt9785/lxt9785e 208-pin pqfp plastic package specification ...............................221 65 intel ? lxt9785/lxt9785e 241-ball bga23 package specs - top/side view (lxt9785bc) .222 66 intel ? lxt9785/lxt9785e 241-ball bga23 package specs - bottom view (lxt9785bc) ....223 67 intel ? lxt9785mbc 196-ball bga15 package spec s - top/side view (lxt9785mbc) ........225 68 ordering information - sample ................................................................................................ .228 tables 1 intel ? lxt9785/lxt9785e signal type descriptions.................................................................20 2 intel ? lxt9785/lxt9785e rmii pqfp pin list ......................................................................... 22 3 intel ? lxt9785/lxt9785e smii pqfp pin list ......................................................................... 27 4 intel ? lxt9785/lxt9785 ss-smii pqfp pin list...................................................................... 32 5 intel ? lxt9785/lxt9785e rmii signal descriptions ? pqfp ................................................... 36 6 intel ? lxt9785/lxt9785e smii / ss-smii common signal descriptions ? pqfp ................... 39 7 intel ? lxt9785/lxt9785e smii specific signal descriptions ? pqfp...................................... 39 8 intel ? lxt9785/lxt9785e ss-smii specific signal descriptions ? pqfp................................ 40 9 intel ? lxt9785/lxt9785e mdio control interface signals ? pqfp......................................... 41 10 intel ? lxt9785/lxt9785e signal detect ? pqfp ..................................................................... 42 11 intel ? lxt9785/lxt9785e network interface signal descriptions ? pqfp............................... 42 12 intel ? lxt9785/lxt9785e jtag test signal descr iptions ? pqfp.......................................... 43 13 intel ? lxt9785/lxt9785e miscellaneous signal descr iptions ? pqfp .................................... 43 14 intel ? lxt9785/lxt9785e led signal descriptions ? pqfp....................................................47 15 intel ? lxt9785/lxt9785e power supply signal descriptions ? pqfp..................................... 48 16 intel ? lxt9785/lxt9785e unused/reserved pins ? pqfp...................................................... 50 17 intel ? lxt9785/lxt9785e receive fifo depth cons iderations............................................... 50
contents 8 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 18 intel? lxt9785/lxt9785e rmii bga23 ball li st in alphanumeric order by signal name ...... 52 19 intel? lxt9785/lxt9785e rmii bga23 ball li st in alphanumeric order by ball location ...... 57 20 intel? lxt9785/lxt9785e smii bga23 ball list in alphanumeric order by signal name....... 62 21 intel? lxt9785/lxt9785e smii bga23 ball list in alphanumeric order by ball location....... 67 22 intel? lxt9785/lxt9785e ss-smii bga23 ball li st in alphanumeric order by signal name. 72 23 intel? lxt9785/lxt9785e ss-smii bga23 ball list in alphanumeric order by ball location. 77 24 intel ? lxt9785/lxt9785e rmii signal descriptions ? bga23 ................................................. 82 25 intel ? lxt9785/lxt9785e smii / ss-smii common si gnal descriptions ? bga23 ................. 85 26 intel ? lxt9785/lxt9785e smii specific signal descriptions ? bga23 .................................... 85 27 intel ? lxt9785/lxt9785e ss-smii s pecific signal descriptions ? bga23 .............................. 86 28 intel ? lxt9785/lxt9785e mdio control interface signals ? bga23 ....................................... 87 29 intel ? lxt9785/lxt9785e signal detect ? bga23 ................................................................... 88 30 intel ? lxt9785/lxt9785e network in terface signal descriptions ? bga23............................. 88 31 intel ? lxt9785/lxt9785e jtag test signal descriptions ? bga23........................................ 89 32 intel ? lxt9785/lxt9785e misc ellaneous signal descriptions ? bga23 .................................. 90 33 intel ? lxt9785/lxt9785e led signal descriptions ? bga23 .................................................. 94 34 intel ? lxt9785/lxt9785e power supp ly signal descriptions ? bga23................................... 95 35 intel ? lxt9785/lxt9785e unused/reserved pins ? bga23 .................................................... 97 36 intel ? lxt9785/lxt9785e receive fifo depth configurations ............................................... 97 37 intel? lxt9785mbc bga15 ball list in alphanu meric order by signal name ......................... 99 38 intel? lxt9785mbc bga15 ball list in alphanumeric order by ball location (smii/ss-smii) ................................................................................................................. ........ 103 39 intel ? lxt9785 bga15 signal descriptions ............. ............................................................... 109 40 intel ? lxt9785/lxt9785e mdix selection ............................................................................. 119 41 intel ? lxt9785/lxt9785e mii mode select ............. ............................................................... 120 42 intel ? lxt9785/9785e global hardware configurat ion settings ............................................. 129 43 intel ? lxt9785/lxt9785e smii signal summary ................................................................... 132 44 intel ? lxt9785/lxt9785e rx status encoding bit definitions ............................................... 137 45 intel ? lxt9785/lxt9785e ss-smii ......................................................................................... 138 46 4b/5b coding ................................................................................................................. .......... 147 47 next page message #5 code word definitions ....................................................................... 155 48 bsr mode of operation ........................................................................................................ ... 159 49 supported jtag instru ctions .................................................................................................. .159 50 intel ? lxt9785/lxt9785e magnetics requirements .............................................................. 166 51 intel ? lxt9785/lxt9785e absolute maximum ratings .......................................................... 173 52 intel ? lxt9785/lxt9785e operating conditions .................................................................... 173 53 intel ? lxt9785/lxt9785e digital i/o dc electrical characteristics (vccio = 2.5 v +/- 5%) . 174 54 intel ? lxt9785/lxt9785e digital i/o dc electrical characteristics (vccio = 3.3 v +/- 5%) . 175 55 intel ? lxt9785/lxt9785e digital i/o dc electrical characteristics ? sd pins ....................... 175 56 intel ? lxt9785/lxt9785e requ ired clock characteristics ..................................................... 175 57 intel ? lxt9785/lxt9785e 100base-tx transceiver characteri stics ............... ............. ........ 176 58 intel ? lxt9785/lxt9785e 100base-fx transceiver characteri stics ............... ............. ........ 176 59 intel ? lxt9785/lxt9785e 10 base-t transceiver characteristic s.............. ................ ........... 177 60 intel ? lxt9785/lxt9785e smii - 100 base-tx receive timing para meters ........... .............. 178 61 intel ? lxt9785/lxt9785e smii - 100base-tx transmit timing parameters ................ ........ 179 62 intel ? lxt9785/lxt9785e smii - 100 base-fx receive timing para meters ........... .............. 180 63 intel ? lxt9785/lxt9785e smii - 100base-fx transmit timing parameters ................ ........ 181 64 intel ? lxt9785/lxt9785e smii - 10base-t receive ti ming parameters ..... ................ ........ 182 65 intel ? lxt9785/lxt9785e smii-10base- t transmit timing parame ters ................ .............. 183 66 intel ? lxt9785/lxt9785e ss- smii - 100base-tx receive timi ng parameters .. ............ ..... 184
datasheet 9 document number: 249241 revision number: 007 revision date: august 28, 2003 contents 67 intel ? lxt9785/lxt9785e ss-smii - 100base-tx tran smit timing......................................185 68 intel ? lxt9785/lxt9785e ss-smii - 100base-fx rece ive timing parameters ...................186 69 intel ? lxt9785/lxt9785e ss-smii - 100base-fx tran smit timing parameters ..................187 70 intel ? lxt9785/lxt9785e ss-smii - 10base-t receive timing para meters ......... ..............188 71 intel ? lxt9785/lxt9785e ss-smii - 10base-t transmit timing parameters .............. ........189 72 intel ? lxt9785/lxt9785e rmii - 100base-tx rece ive timing parameters .............. ...........190 73 intel ? lxt9785/lxt9785e rmii - 1 00base-tx transmit timing pa rameters.......... ..............191 74 intel ? lxt9785/lxt9785e rmii - 100base-fx rece ive timing parameters .............. ...........192 75 intel ? lxt9785/lxt9785e rmii - 1 00base-fx transmit timing pa rameters.......... ..............193 76 intel ? lxt9785/lxt9785e rmii - 10base-t receive timing parameters .. ................ ...........194 77 intel ? lxt9785/lxt9785e rmii - 10 base-t transmit timing parame ters .............. ..............195 78 intel ? lxt9785/lxt9785e auto-negotiat ion and fast link pulse timing parameters............196 79 intel ? lxt9785/lxt9785e mdio timing parameters..............................................................197 80 intel ? lxt9785/lxt9785e power-up timing paramete rs .......................................................198 81 intel ? lxt9785/lxt9785e reset recovery timing parameters .............................................198 82 intel ? lxt9785/lxt9785e register set...................................................................................199 83 control register (address 0) ................................................................................................. ...200 84 status register (address 1).................................................................................................. ....201 85 phy identification register 1 (address 2) ................................................................................203 86 phy identification register 2 (address 3) ................................................................................203 87 auto-negotiation adve rtisement register (address 4) .............................................................204 88 auto-negotiation link partner base page ability register (address 5) ...................................205 89 auto-negotiation expansion register (address 6) ...................................................................206 90 auto-negotiation next page transmit register (address 7) ....................................................206 91 auto-negotiation link partner next page receive register (address 8).................................207 92 port configuration register (a ddress 16, hex 10) ...................................................................207 93 quick status register (address 17, hex 11) ............................................................................209 94 interrupt enable regist er (address 18, hex 12).......................................................................211 95 interrupt status register (addr ess 19, hex 13)........................................................................212 96 led configuration register (address 20, hex 14 ) ...................................................................213 97 receive error count register (address 21, hex 15)................................................................214 98 rmii out-of-band signaling register (address 25, hex 19) ....................................................215 99 trim enable register (address 27, hex 1b)..... ........................................................................216 100 cable diagnostics register (address 29, hex 1d)...................................................................217 101 intel ? lxt9785/lxt9785e register bit map............................................................................219 102 intel? lxt9785mbc 196-ball bga15 package dim ensions ...................................................226 103 product information ......................................................................................................... .........227
contents 10 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 revision history revision number: 007 revision date: august 28, 2003 page description 21 modified figure 2 ?intel? lxt9785 and intel? lxt9785e rmii 208-pin pqfp assignments? . 22 modified table 2 ?intel? lxt9785/lxt9785e rmii pqfp pin list? . 26 modified figure 3 ?intel? lxt9785/lxt9785 e smii 208-pin pqfp assignments? . 27 modified table 3 ?intel? lxt9785/lxt9785e smii pqfp pin list? . 31 modified figure 4 ?intel? lxt9785/lxt9785e ss-smii 208-pin pqfp assignments? . 32 modified table 4 ?intel? lxt9785/lxt9785 ss-smii pqfp pin list? . 36 modified table 5 ?intel? lxt9785/lxt9785e rmii signal descriptions ? pqfp? . 40 modified table 8 ?intel? lxt9785/lxt9785e ss-smii specific signal descriptions ? pqfp? . 43 modified table 13 ?intel? lxt9785/lxt9785e misc ellaneous signal descriptions ? pqfp? . 50 modified table 16 ?intel? lxt9785/lxt9785e unused/reserved pins ? pqfp? . 51 replaced old figures 5, 6, and 7 with figure 5 ?intel? lxt9785/lxt9785e 241-ball bga23 assignments (top view)? . 52 modified table 18 ?intel? lxt9785/lxt9785e rmii bga 23 ball list in alphanumeric order by signal name? . 57 modified table 19 ?intel? lxt9785/lxt9785e rmii bga23 ba ll list in alphanumer ic order by ball location? . 62 modified table 20 ?intel? lxt9785/lxt9785e smii bga 23 ball list in alphanumeric order by signal name? . 67 modified table 21 ?intel? lxt9785/lxt9785e smii bga23 ball list in alphanumeric order by ball location? 72 modified table 22 ?intel? lxt9785/lxt9785e ss-smii bg a23 ball list in alphanumeric order by signal name? . 77 modified table 23 ?intel? lxt9785/lxt9785e ss-smii bg a23 ball list in alphanumeric order by ball location? . 82 modified table 23 ?intel? lxt9785/lxt9785e ss-smii bg a23 ball list in alphanumeric order by ball location? . 86 modified table 27 ?intel? lxt9785/lxt9785e ss-smii specific signal desc riptions ? bga23? . 90 modified table 32 ?intel? lxt9785/lxt9785e misc ellaneous signal descriptions ? bga23? . 97 modified table 35 ?intel? lxt9785/lxt9785e unused/reserved pins ? bga23? . 98 added section 3.5, ?bga15 ball assignments? (including figure 6 ?intel? lxt9785mbc 196-ball bga15 assignments (top view)? , table 37 ?intel? lxt9785mbc bga15 ball list in alphanumeric order by signal name? through table 39 ?intel? lxt9785 bga15 signal descriptions? . 116 added second paragraph under section 4.1, ?introduction? . 117 added note under section 4.1.2.1, ?sectionalization? . 119 added note under table 40 ?intel? lxt9785/lxt9785e mdix selection? . 119 added note under section 4.3, ?media independent interface (mii) interfaces? . 120 added note to table 41 ?intel? lxt9785/lxt9785e mii mode select? .
datasheet 11 document number: 249241 revision number: 007 revision date: august 28, 2003 contents 120 modified/added text under section 4.3.2, ?internal loopback? . 121 modified text under section 4.3.6, ?mii isolate? . 121 section 4.3.7, ?mdio management interface? : added note under second paragraph. added last paragraph. 123 added note under section 4.3.8, ?mii sectionalization? . 124 added new section 4.3.11, ?fifo initial fill values? 125 modified paragraph three under section 4.4.1, ?power requirements? . 127 added notes under second and last paragraphs under section 4.5.3, ?power-down mode? . 128 modified last bullet under section 4.5.3.1, ?global (hardware) power down? . 128 added last paragraph to section 4.5.4, ?reset? . 129 modified table 42 ?intel? lxt9785/9785e global hardware configuration settings? . 130 change heading and modified last line under section 4.6.1.2, ?manual next page exchange? . 130 section 4.6.1.4, ?link criteria? : changed scrambler to descrambler in first line. modified second paragraph. added two new paragraphs. 131 added second paragraph under section 4.6.1.5, ?parallel detection? . 131 modified paragraphs under section 4.6.1.6, ?reliable link es tablishment while auto mdi/mdix is enabled in forced speed mode? . 136 changed ?1110? to ?0101? under section 4.7.4.3, ?receive error? . 141 added note under first paragraph of section 4.8, ?rmii operation? 148 changed ?asynchronously? to ?synchr onously? in second paragraph under section 4.9.3.3, ?carrier sense/data valid (rmii)? . 148 modified last sentence in first paragraph under section 4.9.3.4, ?carrier sense (smii)? . 149 modified paragraph under section 4.9.3.6.3, ?polarity correction? . 149 added note under section 4.9.3.7, ?fiber pmd sublayer? . 149 added second paragraph under section 4.9.3.7.1, ?far end fault indications? . 150 modified/added text under section 4.10.1, ?preamble handling? . 151 modified text under section 4.10.4, ?jabber? . 152 modified first paragraph under section 4.11, ?dte discovery process? . 153 modified item 1 of section 4.11.2, ?interaction between processor, mac, and phy? . 154 modified second paragraph under section 4.11.4, ?dte discovery process flow? . 155 added section 4.11.5, ?dte discovery behavior? 157 added bga15 information into first paragraph under section 4.12.2, ?per-port led driver functions? . 158 added last sentence to first paragr aph and note under first paragraph under section 4.12.3, ?out-of- band signaling? . 160 added section 4.13, ?cable diagnostics overview? . 161 modified/added text under section 4.13.3, ?implementation considerations? . revision number: 007 revision date: august 28, 2003 page description
contents 12 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 162 added section 4.14, ?link hold-off overview? . 173 modified table 52 ?intel? lxt9785/lx t9785e operating conditions? 176 modified table 58 ?intel? lxt9785/lxt9785e 100b ase-fx transceiver characteristics? 178 - 195 added note to table 60 ?intel? lxt9785/lxt9785e smii - 100base-tx receive timing parameters? through table 77 ?intel? lxt9785/lxt9785e rmii - 10base-t transmit timing parameters? . 178 added table note to table 60 ?intel? lxt9785/lxt9785e smii - 100base-tx receive timing parameters? . 184 added table note to table 66 ?intel? lxt9785/lxt9785e ss-smii - 100base-tx receive timing parameters? . 190 added table note to table 72 ?intel? lxt9785/lxt9785e rmii - 100base-tx receive timing parameters? 198 added software power-down and note to table 80 ?intel? lxt9785/lxt9785e power-up timing parameters? . 199 modified paragraphs and added last paragraph under section 7.0, ?register definitions? . 199 modified table 82 ?intel? lxt9785/lxt9785e register set? . 200 modified table 83 ?control register (address 0)? . 201 modified table 84 ?status register (address 1)? . 203 modified table 85 ?phy identification register 1 (address 2)? . 203 modified table 86 ?phy identification register 2 (address 3)? 204 modified table 87 ?auto-negotiation advertisement register (address 4)? 205 modified table 88 ?auto-negotiation link partner base page ability register (address 5)? . 206 modified table 89 ?auto-negotiation expansion register (address 6)? . 206 modified table 90 ?auto-negotiation next page transmit register (address 7)? . 206 modified table 91 ?auto-negotiation link partner next page receive register (address 8)? . 207 modified table 92 ?port configuration register (address 16, hex 10)? . (register bits 16.6, 16.4:3) 209 modified table 93 ?quick status register (address 17, hex 11)? . (register bit 17.8) 211 modified table 94 ?interrupt enable register (address 18, hex 12)? 212 modified table 95 ?interrupt status register (address 19, hex 13)? 213 modified table 96 ?led configuration register (address 20, hex 14)? 214 modified table 97 ?receive error count register (address 21, hex 15)? . 215 modified table 98 ?rmii out-of-band signali ng register (address 25, hex 19)? . 216 modified table 99 ?trim enable register (address 27, hex 1b)? . (register bit 27.6) 217 added table 100 ?cable diagnostics r egister (address 29, hex 1d)? . 219 modified table 101 ?intel? lxt9785/lxt9785e register bit map? . 226 added figure 102 ?intel? lxt9785mbc 196-ball bga15 package dimensions? 227 modified table and figure under section 9.0, ?ordering information? . revision number: 007 revision date: august 28, 2003 page description
datasheet 13 document number: 249241 revision number: 007 revision date: august 28, 2003 contents revision number: 006 (internal release) revision date: june 10, 2003 page description 1 changed "pseudo-ecl (pecl)" to "low voltage po sitive emitter coupled logic (lvpecl)" in the second paragraph, front page. 36 modified table 5 ?intel? lxt9785/lxt9785e rm ii signal descriptions ? pqfp? . added last sentence to rxer0 through rxer7 signal description. 42 modified table 10 ?intel? lxt9785/lxt9785e signal detect ? pqfp? . 42 modified table 11 ?intel? lxt9785/lxt9785e network interface signal descriptions ? pqfp? , 43 modified table 13 ?intel? lxt9785/lxt9785e miscell aneous signal descriptions ? pqfp? . added note to preasel signal description. 116 modified section 4.1, ?introduction? . changed "pseudo-ecl (pecl)" to "low voltage pecl (lvpecl)" in the first paragraph, second sentence. 119 replace text under section 4.2.1.3, ?fiber interface? . 120 modified section 4.3.2, ?internal loopback? . 130 modified last sentence under section 4.6.1.4, ?link criteria? . 131 modified text under section 4.6.1.5, ?parallel detection? . added second paragraph. 136 modified text under section 4.7.4.3, ?receive error? . 145 changed "pecl" to "lvpecl in third paragraph, first sentence under section 4.9.1, ?100base-x network operations? . 146 modified figure 28 ?intel? lxt9785/lxt 9785e protocol sublayers? . 148 modified section 4.9.3.3, ?carrier sense/data valid (rmii)? . changed ?asynchronously to ?synchronously.? 148 modified text under section 4.9.3.4, ?carrier sense (smii)? . revised last sentence in first paragraph. 149 modified paragraph under section 4.9.3.6.3, ?polarity correction? . 149 replaced text under section 4.9.3.7, ?fiber pmd sublayer? . 150 modified section 4.10.1, ?preamble handling? . added text to last paragraph. 151 modified first sentence under section 4.10.4, ?jabber? . 152 modified first paragraph of section 4.11, ?dte discovery process? . 153 modified item 1 of section 4.11.2, ?interaction between processor, mac, and phy? . 158 modified section 4.12.3, ?out-of-band signaling? . added sentence to end of first paragraph. 166 replaced text under section 5.2.5, ?the fiber interface? . 170 replaced figure 36 ?recommended intel? lxt9785/lxt9785e-to-3.3 v fiber transceiver interface circuitry? . 171 replaced figure 37 ?recommended intel? lxt9785/lxt9785e-to-5 v fiber transceiver interface circuitry? . 173 modified table 52 ?intel? lxt9785/lxt9 785e operating conditions? . 174 modified table 53 ?intel? lxt9785/lxt9785e digital i/o dc electrical charac teristics (vccio = 2.5 v +/- 5%)? . 175 modified table 54 ?intel? lxt9785/lxt9785e digital i/o dc electrical charac teristics (vccio = 3.3 v +/- 5%)? . 175 added table 55 ?intel? lxt9785/lxt9785e digital i/o dc electrical characteristics ? sd pins? . 176 modified table 58 ?intel? lxt9785/lxt9785e 100base-fx transceiver characteristics? .
contents 14 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 200 modified table 83 ?control register (address 0)? . 201 modified table 84 ?status register (address 1)? . 204 modified table 87 ?auto-negotiation advertisement register (address 4)? . 205 modified table 88 ?auto-negotiation link partner base page ability register (address 5)? . 207 modified table 91 ?auto-negotiation link partner next page receive register (address 8)? . 207 modified table 92 ?port configuration register (address 16, hex 10)? . 209 modified table 93 ?quick status register (address 17, hex 11)? . 211 modified table 94 ?interrupt enable register (address 18, hex 12)? 212 modified table 95 ?interrupt status register (address 19, hex 13)? . changed all references of ro/ sc to r/lh. 214 modified table 97 ?receive error count register (address 21, hex 15)? . 215 modified table 98 ?rmii out-of-band signali ng register (address 25, hex 19)? . added note to register bit 25.0. 216 modified table 99 ?trim enable register (address 27, hex 1b)? . 227 modified table 103 ?product information? . revision number: 005 revision date: january 2002 page description 1 added bullet to product features 49 modified table 12 ?intel? lxt9785/lxt9785e mi scellaneous signal descriptions? (added fifosel1 and fifosel0) 70 added section 2.6.1.6, ?reliable link establis hment while auto mdi/mdix is enabled in forced speed mode? 109 modified figure 38 ?recommended intel? lxt9785/lxt9785e-to-3.3 v fiber transceiver interface circuitry? 110 added figure 39 ?recommended intel? lxt9785/ lxt9785e-to-5 v fiber transceiver interface circuitry? 111 added figure 40 ?on semiconductor triple pecl-to-lvpecl translator? 112 modified table 28 ?absolute maximum ratings? 112 modified table 29 ?operating conditions? 114 modified table 31 ?digital i/o dc electrical char acteristics (vccio = 3.3 v +/- 5%)?(output low voltage sd pins - max) 129 modified figure 53 ?rmii - 100base-tx receive timing? and table 49 ?rmii - 100base-tx receive timing parameters? 131 modified figure 55 ?rmii - 100base-fx receive timing? and table 51 ?rmii - 100base-fx receive timing parameters? 133 modified figure 57 ?rmii - 10base-t receive timing? and table 53 ?rmii - 10base-t receive timing parameters? revision number: 006 (internal release) revision date: june 10, 2003 page description
datasheet 15 document number: 249241 revision number: 007 revision date: august 28, 2003 contents 146 modified table 69 ?port configuration register (address 16, hex 10)? (bits 16.5 and 16.6) 148 modified table 71 ?interrupt enable register (address 18, hex 12)? 168 added product ordering table and diagram. revision number: 003 revision date: april 2001 page description 1 modified and added new language to front page. 61 reset: modified language in first paragraph. 85 added new section on dte discovery. 93 supported jtag instructions table: replaced long hit streams with hex. 97 led circuit: modified paragraph language. 97 led circuit diagram: modified diagram. 99 replaced typical fiber interface diagram. 102 required clock characteristic s table: replaced smii input frequency and rmii input frequency symbol with ?f?. 122 auto-negotiation and fast link pulse timing parameters: flp burst width under typ = 2. 126 control register table: modified table and table notes. 128 phy identification register 2 (address 3): modified table. 128 phy identifier bit mapping: modified diagram. 131 auto-negotiation expansion: modified table and table notes. 133 port configuration register t able: modified table and table notes. 140 trim enable register: modi fied table (dte discovery). 141 modified register bit map table. revision number: 005 revision date: january 2002 page description
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 18 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 1.0 introduction this document contains information on the intel ? lxt9785/lxt9785e advanced 8-port 10/100 mbps fast ethernet transceivers. 1.1 what you will find in this document this document contains the following sections: ? section 3.0, ?pin/ball assignments and signal descriptions? on page 20 this section contains pin/ball assignments and signal descriptions for the following: ? section 3.1, ?pqfp pin assignments? on page 20 ? section 3.2, ?pqfp signal descriptions? on page 36 ? section 3.3, ?bga23 ball assignments? on page 51 ? section 3.4, ?bga23 signal descriptions? on page 82 ? section 3.5, ?bga15 ball assignments? on page 98 ? section 3.6, ?bga15 signal descriptions? on page 109 ? section 4.0, ?functional description? on page 116 ? section 5.0, ?application information? on page 164 ? section 6.0, ?test specifications? on page 173 ? section 7.0, ?register definitions? on page 199 ? section 8.0, ?package sp ecifications? on page 221 ? section 9.0, ?ordering information? on page 227 1.2 related documents document document number intel ? lxt9785/lxt9785e design and layout guide 249509 intel ? lxt9785/lxt9785e specification update 249357 intel ? lxt9785/lxt9785e 100base-fx fiber opti c transceivers: connecting a pecl/ lvpecl interface 250781 ip telephony and dte disc overy using intel ethernet ? phys 249611
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 19 document number: 249241 revision number: 007 revision date: august 28, 2003 2.0 block diagram figure 1 provides the lxt9785/lxt9785e block diagram. figure 1. intel ? lxt9785/lxt9785e block diagram decoder & descrambler + - + - serial to parallel converter scrambler & encoder txdata n parallel/serial converter carrier sense data valid error detect rxdata n auto negotiation adaptive eq with bl wander cancellation slicer manchester decoder pulse shaper manchester encoder 10 100 10 100 media select port 0 port 1 port 2 port 3 management / mode select logic & led drivers per-port functions tp driver tp / fiber out add_<4:0> mdio mdc mdint port 4 port 5 8-port global functions tx pcs mgmt counters ecl driver tpfon n tpfop n tpfin n tpfip n pwrdn refclk sync (smii only) fiber select n register set register set clock generator clock generator + - 100tx + - 100fx + - 10bt tp / fiber in port 6 port 7 port led drivers led n_<2:0> 3 rx pcs reset 2 2 2 rmii/smii contr
intel ? lxt9785 and intel ? lxt9785e advanced 8-port 10/100 mbps phy transceivers 20 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 3.0 pin/ball assignments and signal descriptions 3.1 pqfp pin assignments the following sections show pqfp pin assignments and signal descriptions: ? section 3.1.1, ?pqfp pin assignments ? rmii configuration? on page 21 ? section 3.1.2, ?pqfp pin assignments ? smii configuration? on page 26 ? section 3.1.3, ?pqfp pin assignments ? ss-smii configuration? on page 31 table 1 lists the acronyms and descriptions for signal types. table 1. intel ? lxt9785/lxt9785e signal type descriptions acronym description ai analog input ao analog output i input o output od open drain output st schmitt triggered input ts three-state-able output sl slew-rate limited output ip weak internal pull-up id weak internal pull-down
intel ? lxt9785 and intel ? lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 21 document number: 249241 revision number: 007 revision date: august 28, 2003 3.1.1 pqfp pin assignments ? rmii configuration figure 2 and table 2, ?intel? lxt9785/lxt9785e rmii pqfp pin list? on page 22 provide lxt9785/lxt9785 rmii pqfp pin assignments. figure 2. intel ? lxt9785 and intel ? lxt9785e rmii 208-pin pqfp assignments crs_dv6.......1 rxer6/linkhold..2 txen6.......3 txdata6_0.......4 txdata6_1.......5 refclk1.......6 rxdata5_1.......7 rxdata5_0.......8 gndio.......9 crs_dv5.......10 rxer5/fifosel1.....11 txen5.......12 txdata5_0.......13 txdata5_1.......14 rxdata4_1.......15 rxdata4_0.......16 crs_dv4.......17 vccio.......18 gndio.......19 rxer4/fifosel0.....20 txen4.......21 txdata4_0.......22 txdata4_1.......23 mdc1.......24 mdio1.......25 mdint1 .......26 rxdata3_1.......27 rxdata3_0.......28 vccio.......29 gndio.......30 crs_dv3.......31 rxer3.......32 txen3.......33 txdata3_0.......34 txdata3_1.......35 rxdata2_1.......36 rxdata2_0.......37 gndio.......38 crs_dv2.......39 rxer2/preasel .....40 txen2.......41 txdata2_0.......42 txdata2_1.......43 refclk0.......44 rxdata1_1.......45 rxdata1_0.......46 vccio.......47 gndio.......48 crs_dv1.......49 rxer1/pause.......50 txen1.......51 txdata1_0.......52 156 .........tpfin7 155 .........gndr7 154 .........tpfop7 153 .........tpfon7 152 .........vcct6/7 151 .........tpfon6 150 .........tpfop6 149 .........gndr6 148 .........gndt6/7 147 .........tpfin6 146 .........tpfip6 145 .........vccr6 144 .........vccr5 143 .........tpfip5 142 .........tpfin5 141 .........gndr5 140 .........tpfop5 139 .........tpfon5 138 .........vcct4/5 137 .........tpfon4 136 .........tpfop4 135 .........gndr4 134 .........gndt4/5 133 .........tpfin4 132 .........tpfip4 131 .........vccr4 130 .........vccr3 129 .........tpfip3 128 .........tpfin3 127 .........gndt2/3 126 .........gndr3 125 .........tpfop3 124 .........tpfon3 123 .........vcct2/3 122 .........tpfon2 121 .........tpfop2 120 .........gndr2 119 .........tpfin2 118 .........tpfip2 117 .........vccr2 116 .........vccr1 115 .........tpfip1 114 .........tpfin1 113 .........gndt0/1 112 .........gndr1 111 .........tpfop1 110 .........tpfon1 109 .........vcct0/1 108 .........tpfon0 107 .........tpfop0 106 .........gndr0 105 .........tpfin0 208 ........ vccio 207 ........ gndio 206 ........ rxdata6_0 205 ........ rxdata6_1 204 ........ txdata7_1 203 ........ txdata7_0 202 ........ txen7 201 ........ rxer7 200 ........ crs_dv7 199 ........ gndio 198 ........ rxdata7_0 197 ........ rxdata7_1 196 ........ vccd 195 ........ gndd 194 ........ led7_3 193 ........ led7_2 192 ........ led7_1 191 ........ led6_3 190 ........ led6_2 189 ........ led6_1 188 ........ gndio 187 ........ led5_3 186 ........ led5_2 185 ........ led5_1 184 ........ vccd 183 ........ gndd 182 ........ led4_3 181 ........ led4_2 180 ........ led4_1 179 ........ sgnd 178 ........ modesel1 177 ........ modesel0 176 ........ section 175 ........ reset 174 ........ pwrdwn 173 ........ g_fx/tp 172 ........ n/c 171....... trst 170 ........ tck 169 ........ tms 168 ........ tdo 167 ........ tdi 166 ........ sd7 165 ........ sd6 164 ........ vccpecl 163 ........ gndpecl 162 ........ sd5 161 ........ sd4 160 ........ n/c 159 ........ n/c 158 ........ vccr7 157 ........ tpfip7 txdata1_1 ...... 53 rxdata0_1 ...... 54 rxdata0_0 ...... 55 vccio ...... 56 gndio ...... 57 crs_dv0 ...... 58 rxer0/mdix ...... 59 txen0 ...... 60 txdata0_0 ...... 61 txdata0_1 ...... 62 mdc0 ...... 63 mdio0 ...... 64 vccd ...... 65 gndd ...... 66 mdint0 ...... 67 led3_3 ...... 68 led3_2 ...... 69 led3_1 ...... 70 led2_3 ...... 71 led2_2 ...... 72 led2_1 ...... 73 gndio ...... 74 led1_3 ...... 75 led1_2 ...... 76 led1_1 ...... 77 vccd ...... 78 gndd ...... 79 led0_3 ...... 80 led0_2 ...... 81 led0_1 ...... 82 amdix_en ...... 83 mddis ...... 84 cfg_3 ...... 85 cfg_2 ...... 86 cfg_1 ...... 87 add_4 ...... 88 add_3 ...... 89 add_2 ...... 90 add_1 ...... 91 add_0 ...... 92 txslew_1 ...... 93 txslew_0 ...... 94 sd_2p5v ...... 95 sd0 ...... 96 sd1 ...... 97 vccpecl ...... 98 gndpecl ...... 99 sd2 ...... 100 sd3 ...... 101 n/c ...... 102 vccr0 ...... 103 tpfip0 ...... 104 lxt9785/9785e xx xxxxxx xxxxxxxx part # lot # fpo # rev #
intel ? lxt9785 and intel ? lxt9785e advanced 8-port 10/100 mbps phy transceivers 22 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 table 2. intel ? lxt9785/lxt9785e rmii pqfp pin list pin symbol type reference for full description 1 crs_dv6 o, ts, sl table 5 (page 36) 2 rxer6/ linkhold o, ts, sl, id, i, st table 5 (page 36) 3 txen6 i, id table 5 (page 36) 4 txdata6_0 i, id table 5 (page 36) 5 txdata6_1 i, id table 5 (page 36) 6 refclk1 i table 5 (page 36) 7 rxdata5_1 o, ts, id table 5 (page 36) 8 rxdata5_0 o, ts table 5 (page 36) 9gndio ? table 15 (page 48) 10 crs_dv5 o, ts, sl table 5 (page 36) 11 rxer5 / fifosel1 o, ts, sl, id, i, st table 5 (page 36) 12 txen5 i, id table 5 (page 36) 13 txdata5_0 i, id table 5 (page 36) 14 txdata5_1 i, id table 5 (page 36) 15 rxdata4_1 o, ts,id table 5 (page 36) 16 rxdata4_0 o, ts table 5 (page 36) 17 crs_dv4 o, ts, sl table 5 (page 36) 18 vccio ? table 15 (page 48) 19 gndio ? table 15 (page 48) 20 rxer4 / fifosel0 o, ts, sl, id, i, st table 5 (page 36) 21 txen4 i, id table 5 (page 36) 22 txdata4_0 i, id table 5 (page 36) 23 txdata4_1 i, id table 5 (page 36) 24 mdc1 i, st, id table 8 (page 40) 25 mdio1 i/o, ts, sl, ip table 8 (page 40) 26 mdint1 od, ts, sl, ip table 8 (page 40) 27 rxdata3_1 o, ts, id table 5 (page 36) 28 rxdata3_0 o, ts table 5 (page 36) 29 vccio ? table 15 (page 48) 30 gndio ? table 15 (page 48) 31 crs_dv3 o, ts, sl table 5 (page 36) 32 rxer3 o, ts, sl, id table 5 (page 36) 33 txen3 i, id table 5 (page 36) 34 txdata3_0 i, id table 5 (page 36) 35 txdata3_1 i, id table 5 (page 36) 36 rxdata2_1 o, ts, id table 5 (page 36) 37 rxdata2_0 o, ts table 5 (page 36) 38 gndio ? table 15 (page 48) 39 crs_dv2 o, ts, sl table 5 (page 36) 40 rxer2 (preasel) o, ts, sl, id, i, st table 5 (page 36) 41 txen2 i, id table 5 (page 36) 42 txdata2_0 i, id table 5 (page 36) 43 txdata2_1 i, id table 5 (page 36) 44 refclk0 i table 5 (page 36) 45 rxdata1_1 o, ts, id table 5 (page 36) 46 rxdata1_0 o, ts table 5 (page 36) 47 vccio ? table 15 (page 48) 48 gndio ? table 15 (page 48) 49 crs_dv1 o, ts, sl table 5 (page 36) 50 rxer1/ pause o, ts, sl, id, i, st table 5 (page 36) 51 txen1 i, id table 5 (page 36) 52 txdata1_0 i, id table 5 (page 36) 53 txdata1_1 i, id table 5 (page 36) 54 rxdata0_1 o, ts, id table 5 (page 36) 55 rxdata0_0 o, ts table 5 (page 36) 56 vccio ? table 15 (page 48) 57 gndio ? table 15 (page 48) 58 crs_dv0 o, ts, sl table 5 (page 36) pin symbol type reference for full description
intel ? lxt9785 and intel ? lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 23 document number: 249241 revision number: 007 revision date: august 28, 2003 59 rxer0/ mdix o, ts, sl, id, i, st table 5 (page 36) 60 txen0 i, id table 5 (page 36) 61 txdata0_0 i, id table 5 (page 36) 62 txdata0_1 i, id table 5 (page 36) 63 mdc0 i, st, id table 8 (page 40) 64 mdio0 i/o, ts, sl, ip table 8 (page 40) 65 vccd ? table 15 (page 48) 66 gndd ? table 15 (page 48) 67 mdint0 od, ts, sl, ip table 8 (page 40) 68 led3_3 od, ts, so, ip table 14 (page 47) 69 led3_2 od, ts, sl, ip table 14 (page 47) 70 led3_1 od, ts, sl, ip table 14 (page 47) 71 led2_3 od, ts, sl, ip table 14 (page 47) 72 led2_2 od, ts, sl, ip table 14 (page 47) 73 led2_1 od, ts, sl, ip table 14 (page 47) 74 gndio ? table 15 (page 48) 75 led1_3 od, ts, sl, ip table 14 (page 47) 76 led1_2 od, ts, sl, ip table 14 (page 47) 77 led1_1 od, ts, sl, ip table 14 (page 47) 78 vccd ? table 15 (page 48) 79 gndd ? table 15 (page 48) 80 led0_3 od, ts, sl, ip table 14 (page 47) 81 led0_2 od, ts, sl, ip table 14 (page 47) 82 led0_1 od, ts, sl, ip table 14 (page 47) 83 amdix_en i, st, ip table 13 (page 43) 84 mddis i, st, id table 9 (page 41) 85 cfg_3 i, st, id table 13 (page 43) 86 cfg_2 i, st, id table 13 (page 43) pin symbol type reference for full description 87 cfg_1 i, st, id table 13 (page 43) 88 add_4 i, st, id table 13 (page 43) 89 add_3 i, st, id table 13 (page 43) 90 add_2 i, st, id table 13 (page 43) 91 add_1 i, st, id table 13 (page 43) 92 add_0 i, st, id table 13 (page 43) 93 txslew_1 i, st, id table 13 (page 43) 94 txslew_0 i, st, id table 13 (page 43) 95 sd_2p5v i, st, id table 10 (page 42) 96 sd0 i table 10 (page 42) 97 sd1 i table 10 (page 42) 98 vccpecl ? table 15 (page 48) 99 gndpecl ? table 15 (page 48) 100 sd2 i table 10 (page 42) 101 sd3 i table 10 (page 42) 102 n/c ? table 17 (page 50) 103 vccr0 ? table 15 (page 48) 104 tpfip0 ao/ai table 11 (page 42) 105 tpfin0 ao/ai table 11 (page 42) 106 gndr0 ? table 15 (page 48) 107 tpfop0 ao/ai table 11 (page 42) 108 tpfon0 ao/ai table 11 (page 42) 109 vcct0/1 ? table 15 (page 48) 110 tpfon1 ao/ai table 11 (page 42) 111 tpfop1 ao/ai table 11 (page 42) 112 gndr1 ? table 15 (page 48) 113 gndt0/1 ? table 15 (page 48) 114 tpfin1 ao/ai table 11 (page 42) 115 tpfip1 ao/ai table 11 (page 42) 116 vccr1 ? table 15 (page 48) 117 vccr2 ? table 15 (page 48) 118 tpfip2 ao/ai table 11 (page 42) 119 tpfin2 ao/ai table 11 (page 42) 120 gndr2 ? table 15 (page 48) 121 tpfop2 ao/ai table 11 (page 42) 122 tpfon2 ao/ai table 11 (page 42) 123 vcct2/3 ? table 15 (page 48) 124 tpfon3 ao/ai table 11 (page 42) pin symbol type reference for full description
intel ? lxt9785 and intel ? lxt9785e advanced 8-port 10/100 mbps phy transceivers 24 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 125 tpfop3 ao/ai table 11 (page 42) 126 gndr3 ? table 15 (page 48) 127 gndt2/3 ? table 15 (page 48) 128 tpfin3 ao/ai table 11 (page 42) 129 tpfip3 ao/ai table 11 (page 42) 130 vccr3 ? table 15 (page 48) 131 vccr4 ? table 15 (page 48) 132 tpfip4 ao/ai table 11 (page 42) 133 tpfin4 ao/ai table 11 (page 42) 134 gndt4/5 ? table 15 (page 48) 135 gndr4 ? table 15 (page 48) 136 tpfop4 ao/ai table 11 (page 42) 137 tpfon4 ao/ai table 11 (page 42) 138 vcct4/5 ? table 15 (page 48) 139 tpfon5 ao/ai table 11 (page 42) 140 tpfop5 ao/ai table 11 (page 42) 141 gndr5 ? table 15 (page 48) 142 tpfin5 ao/ai table 11 (page 42) 143 tpfip5 ao/ai table 11 (page 42) 144 vccr5 ? table 15 (page 48) 145 vccr6 ? table 15 (page 48) 146 tpfip6 ao/ai table 11 (page 42) 147 tpfin6 ao/ai table 11 (page 42) 148 gndt6/7 ? table 15 (page 48) 149 gndr6 ? table 15 (page 48) 150 tpfop6 ao/ai table 11 (page 42) 151 tpfon6 ao/ai table 11 (page 42) 152 vcct6/7 ? table 15 (page 48) 153 tpfon7 ao/ai table 11 (page 42) 154 tpfop7 ao/ai table 11 (page 42) 155 gndr7 ? table 15 (page 48) 156 tpfin7 ao/ai table 11 (page 42) 157 tpfip7 ao/ai table 11 (page 42) 158 vccr7 ? table 15 (page 48) 159 n/c ? table 17 (page 50) 160 n/c ? table 17 (page 50) 161 sd4 i table 10 (page 42) 162 sd5 i table 10 (page 42) pin symbol type reference for full description 163 gndpecl ? table 15 (page 48) 164 vccpecl ? table 15 (page 48) 165 sd6 i table 10 (page 42) 166 sd7 i table 10 (page 42) 167 tdi i, st, ip table 12 (page 43) 168 tdo o, ts table 12 (page 43) 169 tms i, st, ip table 12 (page 43) 170 tck i, st, id table 12 (page 43) 171 trst i, st, ip table 12 (page 43) 172 n/c ? table 17 (page 50) 173 g_fx/tp i, st, id table 13 (page 43) 174 pwrdwn i, st, id table 13 (page 43) 175 reset i, st, ip table 13 (page 43) 176 section i, st, id table 13 (page 43) 177 modesel0 i, st, id table 13 (page 43) 178 modesel1 i, st, id table 13 (page 43) 179 sgnd ? table 15 (page 48) 180 led4_1 od, ts, sl, ip table 14 (page 47) 181 led4_2 od, ts, sl, ip table 14 (page 47) 182 led4_3 od, ts, sl, ip table 14 (page 47) 183 gndd ? table 15 (page 48) 184 vccd ? table 15 (page 48) 185 led5_1 od, ts, sl, ip table 14 (page 47) 186 led5_2 od, ts, sl, ip table 14 (page 47) 187 led5_3 od, ts, sl, ip table 14 (page 47) 188 gndio ? table 15 (page 48) 189 led6_1 od, ts, sl, ip table 14 (page 47) 190 led6_2 od, ts, sl, ip table 14 (page 47) 191 led6_3 od, ts, sl, ip table 14 (page 47) 192 led7_1 od, ts, sl, ip table 14 (page 47) 193 led7_2 od, ts, sl, ip table 14 (page 47) pin symbol type reference for full description
intel ? lxt9785 and intel ? lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 25 document number: 249241 revision number: 007 revision date: august 28, 2003 194 led7_3 od, ts, sl, ip table 5 (page 36) 195 gndd ? table 15 (page 48) 196 vccd ? table 15 (page 48) 197 rxdata7_1 o, ts, id table 5 (page 36) 198 rxdata7_0 o, ts table 5 (page 36) 199 gndio ? table 15 (page 48) 200 crs_dv7 o, ts, sl table 5 (page 36) 201 rxer7 o, ts, sl, id table 5 (page 36) 202 txen7 i, id table 5 (page 36) 203 txdata7_0 i, id table 5 (page 36) 204 txdata7_1 i, id table 5 (page 36) 205 rxdata6_1 o, ts, id table 5 (page 36) 206 rxdata6_0 o, ts table 5 (page 36) 207 gndio ? table 15 (page 48) 208 vccio ? table 15 (page 48) pin symbol type reference for full description
intel ? lxt9785 and intel ? lxt9785e advanced 8-port 10/100 mbps phy transceivers 26 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 3.1.2 pqfp pin assignments ? smii configuration figure 3 and table 3, ?intel? lxt9785/lxt9785e smii pqfp pin list? on page 27 provide the lxt9785/lxt9785e smii pqfp pin assignments. figure 3. intel ? lxt9785/lxt9785e smii 208-pin pqfp assignments n/c.......1 linkhold .......2 n/c.......3 txdata6.......4 n/c.......5 refclk1.......6 n/c.......7 rxdata5.......8 gndio.......9 n/c.......10 fifosel1.......11 n/c.......12 txdata5.......13 n/c.......14 n/c.......15 rxdata4.......16 n/c.......17 vccio.......18 gndio.......19 fifosel0.......20 n/c.......21 txdata4.......22 n/c.......23 mdc1.......24 mdio1.......25 mdint1 .......26 n/c.......27 rxdata3.......28 vccio.......29 gndio.......30 n/c.......31 n/c.......32 n/c.......33 txdata3.......34 sync0.......35 n/c.......36 rxdata2.......37 gndio.......38 n/c.......39 preasel.......40 n/c.......41 txdata2.......42 n/c.......43 refclk0.......44 n/c.......45 rxdata1.......46 vccio.......47 gndio.......48 n/c.......49 pause.......50 n/c.......51 txdata1.......52 156 ........ tpfin7 155 ........ gndr7 154 ........ tpfop7 153 ........ tpfon7 152 ........ vcct6/7 151 ........ tpfon6 150 ........ tpfop6 149 ........ gndr6 148 ........ gndt6/7 147 ........ tpfin6 146 ........ tpfip6 145 ........ vccr6 144 ........ vccr5 143 ........ tpfip5 142 ........ tpfin5 141 ........ gndr5 140 ........ tpfop5 139 ........ tpfon5 138 ........ vcct4/5 137 ........ tpfon4 136 ........ tpfop4 135 ........ gndr4 134 ........ gndt4/5 133 ........ tpfin4 132 ........ tpfip4 131 ........ vccr4 130 ........ vccr3 129 ........ tpfip3 128 ........ tpfin3 127 ........ gndt2/3 126 ........ gndr3 125 ........ tpfop3 124 ........ tpfon3 123 ........ vcct2/3 122 ........ tpfon2 121 ........ tpfop2 120 ........ gndr2 119 ........ tpfin2 118 ........ tpfip2 117 ........ vccr2 116 ........ vccr1 115 ........ tpfip1 114 ........ tpfin1 113 ........ gndt0/1 112 ........ gndr1 111 ........ tpfop1 110 ........ tpfon1 109 ........ vcct0/1 108 ........ tpfon0 107 ........ tpfop0 106 ........ gndr0 105 ........ tpfin0 208 ........ vccio 207 ........ gndio 206 ........ rxdata6 205 ........ n/c 204 ........ sync1 203 ........ txdata7 202 ........ n/c 201 ........ n/c 200 ........ n/c 199 ........ gndio 198 ........ rxdata7 197 ........ n/c 196 ........ vccd 195 ........ gndd 194 ........ led7_3 193 ........ led7_2 192 ........ led7_1 191 ........ led6_3 190 ........ led6_2 189 ........ led6_1 188 ........ gndio 187 ........ led5_3 186 ........ led5_2 185 ........ led5_1 184 ........ vccd 183 ........ gndd 182 ........ led4_3 181 ........ led4_2 180 ........ led4_1 179 ........ sgnd 178 ........ modesel_1 177 ........ modesel_0 176 ........ section 175 ........ reset 174 ........ pwrdwn 173 ........ g_fx/tp 172 ........ n/c 171....... trst 170 ........ tck 169 ........ tms 168 ........ tdo 167 ........ tdi 166 ........ sd7 165 ........ sd6 164 ........ vccpecl 163 ........ gndpecl 162 ........ sd5 161 ........ sd4 160 ........ n/c 159 ........ n/c 158 ........ vccr7 157 ........ tpfip7 n/c ...... 53 n/c ...... 54 rxdata0 ...... 55 vccio ...... 56 gndio ...... 57 n/c ...... 58 mdix ...... 59 n/c ...... 60 txdata0 ...... 61 n/c ...... 62 mdc0 ...... 63 mdio0 ...... 64 vccd ...... 65 gndd ...... 66 mdint0 ...... 67 led3_3 ...... 68 led3_2 ...... 69 led3_1 ...... 70 led2_3 ...... 71 led2_2 ...... 72 led2_1 ...... 73 gndio ...... 74 led1_3 ...... 75 led1_2 ...... 76 led1_1 ...... 77 vccd ...... 78 gndd ...... 79 led0_3 ...... 80 led0_2 ...... 81 led0_1 ...... 82 amdix_en ...... 83 mddis ...... 84 cfg_3 ...... 85 cfg_2 ...... 86 cfg_1 ...... 87 add_4 ...... 88 add_3 ...... 89 add_2 ...... 90 add_1 ...... 91 add_0 ...... 92 txslew_1 ...... 93 txslew_0 ...... 94 sd_2p5v ...... 95 sd0 ...... 96 sd1 ...... 97 vccpecl ...... 98 gndpecl ...... 99 sd2 ...... 100 sd3 ...... 101 n/c ...... 102 vccr0 ...... 103 tpfip0 ...... 104 lxt9785/9785e xx xxxxxx xxxxxxxx part # lot # fpo # rev #
intel ? lxt9785 and intel ? lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 27 document number: 249241 revision number: 007 revision date: august 28, 2003 table 3. intel ? lxt9785/lxt9785e smii pqfp pin list pin symbol type 1 reference for full description 1n/c ? table 16 (page 50) 2 n/c (linkhold) ? i, id, table 16 (page 50) 3n/c ? table 16 (page 50) 4 txdata6 i, id table 6 (page 39) 5n/c ? table 16 (page 50) 6 refclk1 i table 5 (page 36) 7n/c ? table 16 (page 50) 8 rxdata5 o, ts table 6 (page 39) 9 gndio ? table 15 (page 48) 10 n/c ? table 16 (page 50) 11 fifosel1 i, id, st table 16 (page 50) 12 n/c ? table 16 (page 50) 13 txdata5 i, id table 6 (page 39) 14 n/c ? table 16 (page 50) 15 n/c ? table 16 (page 50) 16 rxdata4 o, ts table 6 (page 39) 17 n/c ? table 16 (page 50) 18 vccio ? table 15 (page 48) 19 gndio ? table 15 (page 48) 20 fifosel0 i, id, st table 16 (page 50) 21 n/c i, id table 16 (page 50) 22 txdata4 i, id table 6 (page 39) 23 n/c ? table 16 (page 50) 24 mdc1 i, st, id table 9 (page 41) 25 mdio1 i/o, ts, sl, ip table 9 (page 41) 26 mdint1 od, ts, sl, ip table 9 (page 41) 27 n/c ? table 16 (page 50) 28 rxdata3 o, ts table 6 (page 39) 29 vccio ? table 15 (page 48) 30 gndio ? table 15 (page 48) 31 n/c ? table 16 (page 50) 32 n/c ? table 16 (page 50) 33 n/c ? table 16 (page 50) 34 txdata3 i, id table 6 (page 39) 35 sync0 i, id table 7 (page 39) 36 n/c ? table 16 (page 50) 37 rxdata2 o, ts table 6 (page 39) 38 gndio ? table 15 (page 48) 39 n/c ? table 16 (page 50) 40 preasel i, id, st table 16 (page 50) 41 n/c ? table 16 (page 50) 42 txdata2 i, id table 6 (page 39) 43 n/c ? table 16 (page 50) 44 refclk0 i table 5 (page 36) 45 n/c ? table 16 (page 50) 46 rxdata1 o, ts table 6 (page 39) 47 vccio ? table 15 (page 48) 48 gndio ? table 15 (page 48) 49 n/c ? table 16 (page 50) 50 pause i, id, st table 13 (page 43) 51 n/c ? table 16 (page 50) 52 txdata1 i, id table 6 (page 39) 53 n/c ? table 16 (page 50) 54 n/c ? table 16 (page 50) 55 rxdata0 o, ts table 6 (page 39) 56 vccio ? table 15 (page 48) 57 gndio ? table 15 (page 48) 58 n/c ? table 16 (page 50) 59 mdix i, id, st table 13 (page 43) 60 n/c ? table 16 (page 50) 61 txdata0 i, id table 6 (page 39) 62 n/c ? table 16 (page 50) 63 mdc0 i, st, id table 9 (page 41) 64 mdio0 i/o, ts, sl, ip table 9 (page 41) 65 vccd ? table 15 (page 48) 66 gndd ? table 15 (page 48) 67 mdint0 od, ts, sl, ip table 9 (page 41) pin symbol type 1 reference for full description
intel ? lxt9785 and intel ? lxt9785e advanced 8-port 10/100 mbps phy transceivers 28 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 68 led3_3 od, ts, so, ip table 14 (page 47) 69 led3_2 od, ts, sl, ip table 14 (page 47) 70 led3_1 od, ts, sl, ip table 14 (page 47) 71 led2_3 od, ts, sl, ip table 14 (page 47) 72 led2_2 od, ts, sl, ip table 14 (page 47) 73 led2_1 od, ts, sl, ip table 14 (page 47) 74 gndio ? table 15 (page 48) 75 led1_3 od, ts, sl, ip table 14 (page 47) 76 led1_2 od, ts, sl, ip table 14 (page 47) 77 led1_1 od, ts, sl, ip table 14 (page 47) 78 vccd ? table 15 (page 48) 79 gndd ? table 15 (page 48) 80 led0_3 od, ts, sl, ip table 14 (page 47) 81 led0_2 od, ts, sl, ip table 14 (page 47) 82 led0_1 od, ts, sl, ip table 14 (page 47) 83 amdix_en i, st, ip table 13 (page 43) 84 mddis i, st, id table 8 (page 40) 85 cfg_3 i, st, id table 13 (page 43) 86 cfg_2 i, st, id table 13 (page 43) 87 cfg_1 i, st, id table 13 (page 43) 88 add_4 i, st, id table 13 (page 43) 89 add_3 i, st, id table 13 (page 43) 90 add_2 i, st, id table 13 (page 43) 91 add_1 i, st, id table 13 (page 43) pin symbol type 1 reference for full description 92 add_0 i, st, id table 13 (page 43) 93 txslew_1 i, st, id table 13 (page 43) 94 txslew_0 i, st, id table 13 (page 43) 95 sd_2p5v i, st, id table 10 (page 42) 96 sd0 i table 10 (page 42) 97 sd1 i table 10 (page 42) 98 vccpecl ? table 15 (page 48) 99 gndpecl ? table 15 (page 48) 100 sd2 i table 10 (page 42) 101 sd3 i table 10 (page 42) 102 n/c ? table 17 (page 50) 103 vccr0 ? table 15 (page 48) 104 tpfip0 ai/ao table 11 (page 42) 105 tpfin0 ai/ao table 11 (page 42) 106 gndr0 ? table 15 (page 48) 107 tpfop0 ao/ai table 11 (page 42) 108 tpfon0 ao/ai table 11 (page 42) 109 vcct0/1 ? table 15 (page 48) 110 tpfon1 ao/ai table 11 (page 42) 111 tpfop1 ao/ai table 11 (page 42) 112 gndr1 ? table 15 (page 48) 113 gndt0/1 ? table 15 (page 48) 114 tpfin1 ai/ao table 11 (page 42) 115 tpfip1 ai/ao table 11 (page 42) 116 vccr1 ? table 15 (page 48) 117 vccr2 ? table 15 (page 48) 118 tpfip2 ai/ao table 11 (page 42) 119 tpfin2 ai/ao table 11 (page 42) 120 gndr2 ? table 15 (page 48) 121 tpfop2 ao/ai table 11 (page 42) 122 tpfon2 ao/ai table 11 (page 42) 123 vcct2/3 ? table 15 (page 48) 124 tpfon3 ao/ai table 11 (page 42) 125 tpfop3 ao/ai table 11 (page 42) 126 gndr3 ? table 15 (page 48) 127 gndt2/3 ? table 15 (page 48) 128 tpfin3 ai/ao table 11 (page 42) 129 tpfip3 ai/ao table 11 (page 42) pin symbol type 1 reference for full description
intel ? lxt9785 and intel ? lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 29 document number: 249241 revision number: 007 revision date: august 28, 2003 130 vccr3 ? table 15 (page 48) 131 vccr4 ? table 15 (page 48) 132 tpfip4 ai/ao table 11 (page 42) 133 tpfin4 ai/ao table 11 (page 42) 134 gndt4/5 ? table 15 (page 48) 135 gndr4 ? table 15 (page 48) 136 tpfop4 ao/ai table 11 (page 42) 137 tpfon4 ao/ai table 11 (page 42) 138 vcct4/5 ? table 15 (page 48) 139 tpfon5 ao/ai table 11 (page 42) 140 tpfop5 ao/ai table 11 (page 42) 141 gndr5 ? table 15 (page 48) 142 tpfin5 ai/ao table 11 (page 42) 143 tpfip5 ai/ao table 11 (page 42) 144 vccr5 ? table 15 (page 48) 145 vccr6 ? table 15 (page 48) 146 tpfip6 ai/ao table 11 (page 42) 147 tpfin6 ai/ao table 11 (page 42) 148 gndt6/7 ? table 15 (page 48) 149 gndr6 ? table 15 (page 48) 150 tpfop6 ao/ai table 11 (page 42) 151 tpfon6 ao/ai table 11 (page 42) 152 vcct6/7 ? table 15 (page 48) 153 tpfon7 ao/ai table 11 (page 42) 154 tpfop7 ao/ai table 11 (page 42) 155 gndr7 ? table 15 (page 48) 156 tpfin7 ai/ao table 11 (page 42) 157 tpfip7 ai/ao table 11 (page 42) 158 vccr7 ? table 15 (page 48) 159 n/c ? table 17 (page 50) 160 n/c ? table 17 (page 50) 161 sd4 i table 10 (page 42) 162 sd5 i table 10 (page 42) 163 gndpecl ? table 15 (page 48) 164 vccpecl ? table 15 (page 48) 165 sd6 i table 10 (page 42) 166 sd7 i table 10 (page 42) 167 tdi i, st, ip table 12 (page 43) pin symbol type 1 reference for full description 168 tdo o, ts table 12 (page 43) 169 tms i, st, ip table 12 (page 43) 170 tck i, st, id table 12 (page 43) 171 trst i, st, ip table 12 (page 43) 172 n/c ? table 17 (page 50) 173 g_fx/tp i, st, id table 13 (page 43) 174 pwrdwn i, st, id table 13 (page 43) 175 reset i, st, ip table 13 (page 43) 176 section i, st, id table 13 (page 43) 177 modesel0 i, st, id table 13 (page 43) 178 modesel1 i, st, id table 13 (page 43) 179 sgnd ? table 15 (page 48) 180 led4_1 od, ts, sl, ip table 14 (page 47) 181 led4_2 od, ts, sl, ip table 14 (page 47) 182 led4_3 od, ts, sl, ip table 14 (page 47) 183 gndd ? table 15 (page 48) 184 vccd ? table 15 (page 48) 185 led5_1 od, ts, sl, ip table 14 (page 47) 186 led5_2 od, ts, sl, ip table 14 (page 47) 187 led5_3 od, ts, sl, ip table 14 (page 47) 188 gndio ? table 15 (page 48) 189 led6_1 od, ts, sl, ip table 14 (page 47) 190 led6_2 od, ts, sl, ip table 14 (page 47) 191 led6_3 od, ts, sl, ip table 14 (page 47) 192 led7_1 od, ts, sl, ip table 14 (page 47) pin symbol type 1 reference for full description
intel ? lxt9785 and intel ? lxt9785e advanced 8-port 10/100 mbps phy transceivers 30 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 193 led7_2 od, ts, sl, ip table 14 (page 47) 194 led7_3 od, ts, sl, ip table 5 (page 36) 195 gndd ? table 15 (page 48) 196 vccd ? table 15 (page 48) 197 n/c o, ts, id table 16 (page 50) 198 rxdata7 o, ts table 6 (page 39) 199 gndio ? table 15 (page 48) 200 n/c ? table 16 (page 50) 201 n/c ? table 16 (page 50) 202 n/c ? table 16 (page 50) 203 txdata7 i, id table 6 (page 39) 204 sync1 i, id table 5 (page 36) 205 n/c ? table 16 (page 50) 206 rxdata6 o, ts table 6 (page 39) 207 gndio ? table 15 (page 48) 208 vccio ? table 15 (page 48) pin symbol type 1 reference for full description
intel ? lxt9785 and intel ? lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 31 document number: 249241 revision number: 007 revision date: august 28, 2003 3.1.3 pqfp pin assignments ? ss-smii configuration figure 4 and table 4, ?intel? lxt9785/lxt9785 ss -smii pqfp pin list? on page 32 provide the lxt9785/lxt9785e ss-smii pqfp pin assignments. figure 4. intel ? lxt9785/lxt9785e ss-smii 208-pin pqfp assignments n/c ...... 1 n/clinkhold ...... 2 n/c ...... 3 txdata6 ...... 4 n/c ...... 5 refclk1 ......6 rxdata5 ...... 7 n/c ...... 8 gndio ...... 9 n/c ...... 10 fifosel1 ......11 n/c ...... 12 txdata5 ...... 13 n/c ...... 14 rxdata4 ...... 15 n/c ...... 16 rxsync1 ......17 vccio ......18 gndio ...... 19 fifosel0 ......20 rxclk1 ...... 21 txdata4 ...... 22 n/c ...... 23 mdc1 ......24 mdio1 ...... 25 mdint1 ...... 26 rxdata3 ...... 27 n/c ...... 28 vccio ......29 gndio ...... 30 n/c ...... 31 txclk0 ...... 32 n/c ...... 33 txdata3 ...... 34 txsync0 ......35 rxdata2 ...... 36 n/c ...... 37 gndio ...... 38 n/c ...... 39 preasel ......40 n/c ...... 41 txdata2 ...... 42 n/c ...... 43 refclk0 ......44 rxdata1 ...... 45 n/c ...... 46 vccio ......47 gndio ...... 48 n/c ...... 49 pause ......50 n/c ...... 51 txdata1 ...... 52 156......... tpfin7 155......... gndr7 154.........tpfop7 153......... tpfon7 152.........vcct6/7 151......... tpfon6 150.........tpfop6 149......... gndr6 148......... gndt6/7 147......... tpfin6 146.........tpfip6 145.........vccr6 144.........vccr5 143.........tpfip5 142......... tpfin5 141......... gndr5 140.........tpfop5 139......... tpfon5 138.........vcct4/5 137......... tpfon4 136.........tpfop4 135......... gndr4 134......... gndt4/5 133......... tpfin4 132.........tpfip4 131.........vccr4 130.........vccr3 129.........tpfip3 128......... tpfin3 127......... gndt2/3 126......... gndr3 125.........tpfop3 124......... tpfon3 123.........vcct2/3 122......... tpfon2 121.........tpfop2 120......... gndr2 119......... tpfin2 118.........tpfip2 117.........vccr2 116.........vccr1 115.........tpfip1 114......... tpfin1 113......... gndt0/1 112......... gndr1 111.........tpfop1 110......... tpfon1 109.........vcct0/1 108......... tpfon0 107.........tpfop0 106......... gndr0 105......... tpfin0 208 ......... vccio 207 ......... gndio 206 ......... n/c 205 ......... rxdata6 204 ......... txsync1 203 ......... txdata7 202 ......... n/c 201 ......... txclk1 200 ......... n/c 199 ......... gndio 198 ......... n/c 197 ......... rxdata7 196 .........vccd 195 ......... gndd 194 ......... led7_3 193 ......... led7_2 192 ......... led7_1 191 ......... led6_3 190 ......... led6_2 189 ......... led6_1 188 ......... gndio 187 ......... led5_3 186 ......... led5_2 185 ......... led5_1 184 ......... vccd 183 ......... gndd 182 ......... led4_3 181 ......... led4_2 180 ......... led4_1 179 ......... sgnd 178 ......... modesel_1 177 ......... modesel_0 176 ......... section 175 ......... reset 174 ......... pwrdwn 173 ......... g_fx/tp 172 ......... n/c 171....... trst 170 ......... tck 169 ......... tms 168 ......... tdo 167 ......... tdi 166 ......... sd7 165 ......... sd6 164 ......... vccpecl 163 ......... gndpecl 162 ......... sd5 161 ......... sd4 160 ......... n/c 159 ......... n/c 158 ......... vccr7 157 ......... tpfip7 n/c...... 53 rxdata0...... 54 n/c...... 55 vccio...... 56 gndio...... 57 rxsync0...... 58 mdix...... 59 rxclk0...... 60 txdata0...... 61 n/c...... 62 mdc0...... 63 mdio0...... 64 vccd...... 65 gndd...... 66 mdint0 ...... 67 led3_3 ...... 68 led3_2 ...... 69 led3_1 ...... 70 led2_3 ...... 71 led2_2 ...... 72 led2_1 ...... 73 gndio...... 74 led1_3 ...... 75 led1_2 ...... 76 led1_1 ...... 77 vccd...... 78 gndd...... 79 led0_3 ...... 80 led0_2 ...... 81 led0_1 ...... 82 amdix_en...... 83 mddis...... 84 cfg_3...... 85 cfg_2...... 86 cfg_1...... 87 add_4...... 88 add_3...... 89 add_2...... 90 add_1...... 91 add_0...... 92 txslew_1...... 93 txslew_0...... 94 sd_2p5v...... 95 sd0...... 96 sd1...... 97 vccpecl...... 98 gndpecl...... 99 sd2...... 100 sd3...... 101 n/c...... 102 vccr0...... 103 tpfip0...... 104 lxt9785/9785e xx xxxxxx xxxxxxxx part # lot # fpo # rev #
intel ? lxt9785 and intel ? lxt9785e advanced 8-port 10/100 mbps phy transceivers 32 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 table 4. intel ? lxt9785/lxt9785 ss-smii pqfp pin list pin symbol type 1 reference for full description 1n/c ? table 16 (page 50) 2 n/c linkhold table 13 (page 43) 3n/c ? table 16 (page 50) 4 txdata6 i, id table 6 (page 39) 5n/c i table 16 (page 50) 6 refclk1 i table 6 (page 39) 7 rxdata5 o, ts, id table 8 (page 40) 8n/c ? table 16 (page 50) 9 gndio ? table 15 (page 48) 10 n/c ? table 16 (page 50) 11 fifosel1 i, id, st table 13 (page 43) 12 n/c ? table 16 (page 50) 13 txdata5 i, id table 6 (page 39) 14 n/c ? table 16 (page 50) 15 rxdata4 o, ts, id table 8 (page 40) 16 n/c ? table 16 (page 50) 17 rxsync1 o, ts, id table 8 (page 40) 18 vccio ? table 15 (page 48) 19 gndio ? table 15 (page 48) 20 fifosel0 i, id, st table 13 (page 43) 21 rxclk1 o, ts, id table 8 (page 40) 22 txdata4 i, id table 6 (page 39) 23 n/c ? table 16 (page 50) 24 mdc1 i, st, id table 9 (page 41) 25 mdio1 i/o, ts, sl, ip table 9 (page 41) 26 mdint1 od, ts, sl, ip table 9 (page 41) 27 rxdata3 o, ts, id table 8 (page 40) 28 n/c ? table 16 (page 50) 29 vccio ? table 15 (page 48) 30 gndio ? table 15 (page 48) 31 n/c ? table 16 (page 50) 32 txclk0 i, id table 8 (page 40) 33 n/c ? table 16 (page 50) 34 txdata3 i, id table 6 (page 39) 35 txsync0 i, id table 8 (page 40) 36 rxdata2 o, ts, id table 8 (page 40) 37 n/c ? table 16 (page 50) 38 gndio ? table 15 (page 48) 39 n/c ? table 16 (page 50) 40 preasel i, st table 13 (page 43) 41 n/c ? table 16 (page 50) 42 txdata2 i, id table 6 (page 39) 43 n/c ? table 16 (page 50) 44 refclk0 i table 6 (page 39) 45 rxdata1 o, ts, id table 8 (page 40) 46 n/c ? table 16 (page 50) 47 vccio ? table 15 (page 48) 48 gndio ? table 15 (page 48) 49 n/c ? table 16 (page 50) 50 pause i, id, st table 13 (page 43) 51 n/c ? table 16 (page 50) 52 txdata1 i, id table 6 (page 39) 53 n/c ? table 16 (page 50) 54 rxdata0 o, ts, id table 8 (page 40) 55 n/c ? table 16 (page 50) 56 vccio ? table 15 (page 48) 57 gndio ? table 15 (page 48) 58 rxsync0 o, ts, id table 8 (page 40) 59 mdix i, id, st table 13 (page 43) 60 rxclk0 ? table 8 (page 40) 61 txdata0 i, id table 6 (page 39) 62 n/c ? table 16 (page 50) 63 mdc0 i, st, id table 9 (page 41) 64 mdio0 i/o, ts, sl, ip table 9 (page 41) 65 vccd ? table 15 (page 48) 66 gndd ? table 15 (page 48) pin symbol type 1 reference for full description
intel ? lxt9785 and intel ? lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 33 document number: 249241 revision number: 007 revision date: august 28, 2003 67 mdint0 od, ts, sl, ip table 9 (page 41) 68 led3_3 od, ts, so, ip table 14 (page 47) 69 led3_2 od, ts, sl, ip table 14 (page 47) 70 led3_1 od, ts, sl, ip table 14 (page 47) 71 led2_3 od, ts, sl, ip table 14 (page 47) 72 led2_2 od, ts, sl, ip table 14 (page 47) 73 led2_1 od, ts, sl, ip table 14 (page 47) 74 gndio ? table 15 (page 48) 75 led1_3 od, ts, sl, ip table 14 (page 47) 76 led1_2 od, ts, sl, ip table 14 (page 47) 77 led1_1 od, ts, sl, ip table 14 (page 47) 78 vccd ? table 15 (page 48) 79 gndd ? table 15 (page 48) 80 led0_3 od, ts, sl, ip table 14 (page 47) 81 led0_2 od, ts, sl, ip table 14 (page 47) 82 led0_1 od, ts, sl, ip table 14 (page 47) 83 amdix_en i, st, ip table 13 (page 43) 84 mddis i, st, id table 9 (page 41) 85 cfg_3 i, st, id table 13 (page 43) 86 cfg_2 i, st, id table 13 (page 43) 87 cfg_1 i, st, id table 13 (page 43) 88 add_4 i, st, id table 13 (page 43) 89 add_3 i, st, id table 13 (page 43) 90 add_2 i, st, id table 13 (page 43) 91 add_1 i, st, id table 13 (page 43) 92 add_0 i, st, id table 13 (page 43) 93 txslew_1 i, st, id table 13 (page 43) 94 txslew_0 i, st, id table 13 (page 43) 95 sd_2p5v i, st, id table 10 (page 42) 96 sd0 i table 10 (page 42) pin symbol type 1 reference for full description 97 sd1 i table 10 (page 42) 98 vccpecl ? table 15 (page 48) 99 gndpecl ? table 15 (page 48) 100 sd2 i table 10 (page 42) 101 sd3 i table 10 (page 42) 102 n/c ? table 16 (page 50) 103 vccr0 ? table 15 (page 48) 104 tpfip0 ai/ao table 11 (page 42) 105 tpfin0 ai/ao table 11 (page 42) 106 gndr0 ? table 15 (page 48) 107 tpfop0 ao/ai table 11 (page 42) 108 tpfon0 ao/ai table 11 (page 42) 109 vcct0/1 ? table 15 (page 48) 110 tpfon1 ao/ai table 11 (page 42) 111 tpfop1 ao/ai table 11 (page 42) 112 gndr1 ? table 15 (page 48) 113 gndt0/1 ? table 15 (page 48) 114 tpfin1 ai/ao table 11 (page 42) 115 tpfip1 ai/ao table 11 (page 42) 116 vccr1 ? table 15 (page 48) 117 vccr2 ? table 15 (page 48) 118 tpfip2 ai/ao table 11 (page 42) 119 tpfin2 ai/ao table 11 (page 42) 120 gndr2 ? table 15 (page 48) 121 tpfop2 ao/ai table 11 (page 42) 122 tpfon2 ao/ai table 11 (page 42) 123 vcct2/3 ? table 15 (page 48) 124 tpfon3 ao/ai table 11 (page 42) 125 tpfop3 ao/ai table 11 (page 42) 126 gndr3 ? table 15 (page 48) 127 gndt2/3 ? table 15 (page 48) 128 tpfin3 ai/ao table 11 (page 42) 129 tpfip3 ai/ao table 11 (page 42) 130 vccr3 ? table 15 (page 48) 131 vccr4 ? table 15 (page 48) 132 tpfip4 ai/ao table 11 (page 42) 133 tpfin4 ai/ao table 11 (page 42) 134 gndt4/5 ? table 15 (page 48) pin symbol type 1 reference for full description
intel ? lxt9785 and intel ? lxt9785e advanced 8-port 10/100 mbps phy transceivers 34 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 135 gndr4 ? table 15 (page 48) 136 tpfop4 ao/ai table 11 (page 42) 137 tpfon4 ao/ai table 11 (page 42) 138 vcct4/5 ? table 15 (page 48) 139 tpfon5 ao/ai table 11 (page 42) 140 tpfop5 ao/ai table 11 (page 42) 141 gndr5 ? table 15 (page 48) 142 tpfin5 ai/ao table 11 (page 42) 143 tpfip5 ai/ao table 11 (page 42) 144 vccr5 ? table 15 (page 48) 145 vccr6 ? table 15 (page 48) 146 tpfip6 ai/ao table 11 (page 42) 147 tpfin6 ai/ao table 11 (page 42) 148 gndt6/7 ? table 15 (page 48) 149 gndr6 ? table 15 (page 48) 150 tpfop6 ao/ai table 11 (page 42) 151 tpfon6 ao/ai table 11 (page 42) 152 vcct6/7 ? table 15 (page 48) 153 tpfon7 ao/ai table 11 (page 42) 154 tpfop7 ao/ai table 11 (page 42) 155 gndr7 ? table 15 (page 48) 156 tpfin7 ai/ao table 11 (page 42) 157 tpfip7 ai/ao table 11 (page 42) 158 vccr7 ? table 15 (page 48) 159 n/c ? table 16 (page 50) 160 n/c ? table 16 (page 50) 161 sd4 i table 10 (page 42) 162 sd5 i table 10 (page 42) 163 gndpecl ? table 15 (page 48) 164 vccpecl ? table 15 (page 48) 165 sd6 i table 10 (page 42) 166 sd7 i table 10 (page 42) 167 tdi i, st, ip table 12 (page 43) 168 tdo o, ts table 12 (page 43) 169 tms i, st, ip table 12 (page 43) 170 tck i, st, id table 12 (page 43) 171 trst i, st, ip table 12 (page 43) 172 n/c ? table 16 (page 50) pin symbol type 1 reference for full description 173 g_fx/tp i, st, id table 13 (page 43) 174 pwrdwn i, st, id table 13 (page 43) 175 reset i, st, ip table 13 (page 43) 176 section i, st, id table 13 (page 43) 177 modesel0 i, st, id table 13 (page 43) 178 modesel1 i, st, id table 13 (page 43) 179 sgnd ? table 15 (page 48) 180 led4_1 od, ts, sl, ip table 14 (page 47) 181 led4_2 od, ts, sl, ip table 14 (page 47) 182 led4_3 od, ts, sl, ip table 14 (page 47) 183 gndd ? table 15 (page 48) 184 vccd ? table 15 (page 48) 185 led5_1 od, ts, sl, ip table 14 (page 47) 186 led5_2 od, ts, sl, ip table 14 (page 47) 187 led5_3 od, ts, sl, ip table 14 (page 47) 188 gndio ? table 15 (page 48) 189 led6_1 od, ts, sl, ip table 14 (page 47) 190 led6_2 od, ts, sl, ip table 14 (page 47) 191 led6_3 od, ts, sl, ip table 14 (page 47) 192 led7_1 od, ts, sl, ip table 14 (page 47) 193 led7_2 od, ts, sl, ip table 14 (page 47) 194 led7_3 od, ts, sl, ip table 14 (page 47) 195 gndd ? table 15 (page 48) 196 vccd ? table 15 (page 48) 197 rxdata7 o, ts, id table 8 (page 40) 198 n/c ? table 16 (page 50) 199 gndio ? table 15 (page 48) 200 n/c ? table 16 (page 50) 201 txclk1 i, id table 8 (page 40) 202 n/c ? table 16 (page 50) pin symbol type 1 reference for full description
intel ? lxt9785 and intel ? lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 35 document number: 249241 revision number: 007 revision date: august 28, 2003 203 txdata7 i, id table 6 (page 39) 204 txsync1 i, id table 8 (page 40) 205 rxdata6 o, ts, id table 8 (page 40) 206 n/c ? table 16 (page 50) 207 gndio ? table 15 (page 48) 208 vccio ? table 15 (page 48) pin symbol type 1 reference for full description
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 36 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 3.2 pqfp signal descriptions 3.2.1 signal name conventions signal names may contain either a port designation or a serial designation, or a combination of the two designations. signal naming conventions are as follows: ? port number only. individual signals that apply to a particular port are designated by the signal mnemonic, immediately fo llowed by the port designa tion. for example, transmit enable signals would be identified as txen0, txen1, and txen2. ? serial number only. a set of signals which are not tied to any specific port are designated by the signal mnemonic, fo llowed by an underscore and a serial designation. for example, a set of three global configuration signals would be identified as cfg_1, cfg_2, and cfg_3. ? port and serial number. in cases where each port is assigned a set of multiple signals, each signal is designated in the following order: signal mnemonic, port designation, an underscore, and the serial designation. for exam ple, a set of three port configuration signals would be identified as rxdata0_0 and rxdata0_1, rxdata1_0 and rxdata1_1, and rxdata2_0 and rxdata2_1. 3.2.2 pqfp signal descriptions ? rmii, smii, and ss-smii configurations table 5 through table 17, ?intel? lxt9785/ lxt9785e receive fifo depth considerations? on page 50 provide pqfp signal descriptions. ball designations are included for cross-reference. table 5. intel ? lxt9785/lxt9785e rmii signal descriptions ? pqfp (sheet 1 of 3) pin-ball designation symbol type 1 signal description 2,3 pqfp pbga 44 6 e6, e12 refclk0 refclk1 i reference clock. 50 mhz rmii reference clock is always required. rmii inputs are sampled on the rising edge of refclk, rmii outputs are sourced on the falling edge. see ?clock/sync requir ements? on page 125 for detailed clk requirements. 61 62 e2, f4 txdata0_0 txdata0_1 i, id transmit data - port 0. inputs containing 2-bit parall el di-bits to be transmitted from port 0 are clocked in synchronously to refclk. 52 53 c3, d4 txdata1_0 txdata1_1 i, id transmit data - port 1. inputs containing 2-bit parall el di-bits to be transmitted from port 1 are clocked in synchronously to refclk 42 43 b5 a4 txdata2_0 txdata2_1 i, id transmit data - port 2. inputs containing 2-bit parall el di-bits to be transmitted from port 2 are clocked in synchronously to refclk. 1. type column coding: i = input, o = output, od = open drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull- down. 2. the ip/id resistors are disabled during h/w power-down mode. if a pin is an output or an i/o, the ip/id resistors are also disabled when the output is enabled. 3. rxdata[0:7]_0, rxdata[0:7]_1, crs_dv[0:7] and rxer[0:7] outputs are three-stated in isolation and h/w power-down modes and during h/w reset.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 37 document number: 249241 revision number: 007 revision date: august 28, 2003 34 35 d8, a6 txdata3_0 txdata3_1 i, id transmit data - port 3. inputs containing 2-bit parallel di-bits to be transmitted from port 3 are clocked in synchronously to refclk. 22 23 a11, c10 txdata4_0 txdata4_1 i, id transmit data - port 4. inputs containing 2-bit parallel di-bits to be transmitted from port 4 are clocked in synchronously to refclk. 13 14 b13, d11 txdata5_0 txdata5_1 i, id transmit data - port 5. inputs containing 2-bit parallel di-bits to be transmitted from port 5 are clocked in synchronously to refclk. 4 5 d13, a16 txdata6_0 txdata6_1 i, id transmit data - port 6. inputs containing 2-bit parallel di-bits to be transmitted from port 6 are clocked in synchronously to refclk. 203 204 e14, c16 txdata7_0 txdata7_1 i, id transmit data - port 7. inputs containing 2-bit parallel di-bits to be transmitted from port 7 are clocked in synchronously to refclk. 60 51 41 33 21 12 3 202 e3, b2, c6, a7, b11, a14, c14, d16 txen0 txen1 txen2 txen3 txen4 txen5 txen6 txen7 i, id transmit enable - ports 0-7. active high input enables respective port transmitter. this signal must be synchronous to the refclk. 55 54 c2, b1 rxdata0_0 rxdata0_1 o, ts o, ts, id receive data - port 0. receive data signals (2-bit pa rallel di-bits) are driven synchronously to refclk. 46 45 a3, b4 rxdata1_0 rxdata1_1 o, ts o, ts, id receive data - port 1. receive data signals (2-bit pa rallel di-bits) are driven synchronously to refclk. 37 36 b6, c7 rxdata2_0 rxdata2_1 o, ts o, ts, id receive data - port 2. receive data signals (2-bit pa rallel di-bits) are driven synchronously to refclk. 28 27 d9, b9 rxdata3_0 rxdata3_1 o, ts o, ts, id receive data - port 3. receive data signals (2-bit pa rallel di-bits) are driven synchronously to refclk. 16 15 a13, c12 rxdata4_0 rxdata4_1 o, ts o, ts, id receive data - port 4. receive data signals (2-bit pa rallel di-bits) are driven synchronously to refclk. 8 7 b14, b15 rxdata5_0 rxdata5_1 o, ts o, ts, id receive data - port 5. receive data signals (2-bit pa rallel di-bits) are driven synchronously to refclk. table 5. intel ? lxt9785/lxt9785e rmii signal descriptions ? pqfp (sheet 2 of 3) pin-ball designation symbol type 1 signal description 2,3 pqfp pbga 1. type column coding: i = input, o = output, od = o pen drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull- down. 2. the ip/id resistors are disabled during h/w power-do wn mode. if a pin is an output or an i/o, the ip/id resistors are also disabled when the output is enabled. 3. rxdata[0:7]_0, rxdata[0:7]_1, crs_dv[0:7] and rxer[0:7] outputs are three-stated in isolation and h/w power-down modes and during h/w reset.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 38 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 206 205 c15, b17 rxdata6_0 rxdata6_1 o, ts o, ts, id receive data - port 6. receive data signals (2-bit pa rallel di-bits) are driven synchronously to refclk. 198 197 e16, f14 rxdata7_0 rxdata7_1 o, ts o, ts, id receive data - port 7. receive data signals (2-bit pa rallel di-bits) are driven synchronously to refclk. 58 49 39 31 17 10 1 200 e4, c4, a5, b8, b12, d12, b16, e15 crs_dv0 crs_dv1 crs_dv2 crs_dv3 crs_dv4 crs_dv5 crs_dv6 crs_dv7 o, ts, sl, id carrier sense/receive data valid - ports 0-7. on detection of valid carrier, these signals are asserted asynchronously with respect to refclk. crs_dvn is de-asserted on loss of carrier, synchronous to refclk. 59 50 40 32 20 11 2 201 d2, d5, d7, c8, a12, a15, a17, d17 rxer0 rxer1 rxer2 rxer3 rxer4 rxer5 rxer6 rxer7 o, ts, sl, id receive error - ports 0-7. these signals are synchro nous to the respective refclk. active high indicates that received code group is invalid, or that pll is not locked. the rxer signals have the following additional function pins: rxer0 (mdix) rxer1 (pause) rxer2 (preasel) rxer4 (fifosel0) rxer5 (fifosel1) rxer6 (linkhold) table 5. intel ? lxt9785/lxt9785e rmii signal descriptions ? pqfp (sheet 3 of 3) pin-ball designation symbol type 1 signal description 2,3 pqfp pbga 1. type column coding: i = input, o = output, od = open drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull- down. 2. the ip/id resistors are disabled during h/w power-down mode. if a pin is an output or an i/o, the ip/id resistors are also disabled when the output is enabled. 3. rxdata[0:7]_0, rxdata[0:7]_1, crs_dv[0:7] and rxer[0:7] outputs are three-stated in isolation and h/w power-down modes and during h/w reset.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 39 document number: 249241 revision number: 007 revision date: august 28, 2003 table 6. intel ? lxt9785/lxt9785e smii / ss-smii common signal descriptions ? pqfp pin/ball designation symbol type 1 signal description 2 pqfp pbga 61 52 42 34 22 13 4 203 e2, c3, b5, d8, a11, b13, d13, e14 txdata0 txdata1 txdata2 txdata3 txdata4 txdata5 txdata6 txdata7 i, id transmit data - ports 0-7. these serial input streams provide data to be transmitted to the network. the lxt9785/9785e clocks the data in synchronously to refclk. 44 6 e6, e12 refclk0 refclk1 i reference clock. the lxt9785/9785e always requires a 125 mhz reference clock input. refer to functional description for detailed clock requirements. refclk0 and refclk1 are always connected regardless of sectionalization mode. 1. type column coding: i = input, o = output, od = o pen drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull- down. 2. the ip/id resistors are disabled during h/w power-down mode. table 7. intel ? lxt9785/lxt9785e smii specific signal descriptions ? pqfp pin/ball designation symbol type 1 signal description 2,3 pqfp pbga 35 204 a6, c16 sync0 sync1 i, id smii synchronization. the mac must generate a sync pulse every 10 refclk cycles to synchronize the smii. sync0 is used when 1x8 port sectionalization is selected. sync0 and sync1 are to be used when 2x4 port sectionalization is chosen. 55 46 37 28 16 8 206 198 c2, a3, b6, d9, a13, b14, c15, e16 rxdata0 rxdata1 rxdata2 rxdata3 rxdata4 rxdata5 rxdata6 rxdata7 o, ts receive data - ports 0-7 . these serial output streams provide data received from the network. the lxt9785/9785e drives the data out synchronously to refclk. 1. type column coding: i = input, o = output, od = o pen drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull- down. 2. the ip/id resistors are disabled during h/w power-down mode. 3. rxdata[0:7] outputs are three-stated in isolation and hardware power-down modes and during hardware reset.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 40 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 table 8. intel ? lxt9785/lxt9785e ss-smii specif ic signal descriptions ? pqfp pin/ball designation symbol type 1 signal description 2,3 pqfp pbga 35 204 a6, c16 txsync0 txsync1 i, id ss-smii transmit synchronization. the mac must generate a txsync pulse every 10 txclk cycles to mark the start of txdata segments. txsync0 is used when 1x8 port sectionalization is selected. 58 17 e4, b12 rxsync0 rxsync1 o, ts, id ss-smii receive synchronization. the lxt9785/9785e generates these pulses every 10 rxclk cycles to mark the start of rxdata segments for the mac. rxsync1 is used when 1x8 port secti onalization is selected. rxsync0 may not be used. these outputs are only enabled when ss-smii mode is enabled. 32 201 c8, d17 txclk0 txclk1 i, id ss-smii transmit clock. the mac sources this 125 mhz clock as the timing reference for txdata and txsync. only txclk0 is used when 1x8 port sectionalization is selected. see ?clock/ sync requirements? on page 125 for detailed clock requirements. 60 21 e3, b11 rxclk0 rxclk1 o, ts, id ss-smii receive clock. the lxt9785/9785e generates these clocks, based on refclk, to provide a timing reference for rxdata and rxsync to the mac. rxclk1 is used when 1x8 port sectionalization is selected. rxclk0 may not be used. see ?clock/sync requirements? on page 125 for detailed clock requirements . these outputs are only enabled when ss- smii mode is enabled. 54 45 36 27 15 7 205 197 b1, b4, c7, b9, c12, b15, b17, f14 rxdata0 rxdata1 rxdata2 rxdata3 rxdata4 rxdata5 rxdata6 rxdata7 o, ts, id receive data - ports 0-7. these serial output streams provide data received from the network. the lxt9785/9785e drives the data out synchronously to refclk. 1. type column coding: i = input, o = output, od = open drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull- down. 2. the ip/id resistors are disabled during h/w power-down mode. if a pin is an output or an i/o, the ip/id resistors are also disabled when the output is enabled. 3. rxdata[0:7], rxsync[0:1], and rxclk[0:1] outputs are three-stated in isolation and h/w power-down modes and during h/w reset.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 41 document number: 249241 revision number: 007 revision date: august 28, 2003 table 9. intel ? lxt9785/lxt9785e mdio control interface signals ? pqfp pin/ball designation symbol type 1 signal description 2,3, 4 pqfp pbga 64 25 f3, a10 mdio0 mdio1 i/o, ts, sl, ip management data input/output. bidirectional serial data channel for communication between the phy and mac or switch asic. only mdio0 is used when 1x8 port sectionalization is selected. in 2x4 port sectionalization mode, mdio0 accesses ports 0-3 and mdio1 accesses ports 4-7. refer to figure 21 on page 140 . 67 26 f1, c9 mdint0 mdint1 od,ts, sl, ip management data interrupt. when register bit 18.1 = 1, an active low output on this pin indicates status change. only mdint0 is used when 1x8 port sectionalizat ion is selected. in 2x4 port sectionalization mode, mdint0 is associated with ports 0-3 and mdint1 is associated with ports 4-7. refer to figure 21 on page 140 . 63 24 e1, b10 mdc0 mdc1 i, st, id management data clock. clock for the mdio serial data channel. maximum frequency is 20 mhz. only m dc0 is used when 1x8 port sectionalization is selected. in 2x4 port sectionalization mode, mdc0 clocks ports 0-3 register accesses and mdc1 clocks por ts 4-7 register accesses. refer to figure 21 on page 140 . 84 l1 mddis i, st, id management disable. when mddis is tied high, the mdio port is completely disabled and the hardware control interface pins set their respective bits at power up and reset. when mddis is pulled low at power up or reset, via the internal pull-down resistor or by tieing it to ground, the hardware control interface pins control only the initial or ?default? values of their re spective register bits. after the power-up/reset cycle is complete, bit control reverts to the mdio serial channel. 1. type column coding: i = input, o = output, od = o pen drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull- down. 2. the ip/id resistors are disabled during h/w power-do wn mode. if a pin is an output or an i/o, the ip/id resistors are also disabled when the output is enabled. 3. mdio[0:1] and mdint [0:1] outputs are three-stated in h/w power-down mode and during h/w reset. 4. supports the 802.3 mdio register set. specific bits in the registers are referenc ed using an ?x.y? notation, where x is the register number (0-32) and y is the bit number (0-15).
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 42 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 table 10. intel ? lxt9785/lxt9785e signal detect ? pqfp pin/ball designation symbol type 1 signal description 2,3 pqfp pbga 95 p1 sd_2p5v i, st, id signal detect 2.5 volt interface. sd input threshold voltage select. tie to vccpecl = select 2.5 v lvpecl input levels float or tie to gndpecl = select 3.3 v lvpecl input levels 96 97 100 101 161 162 165 166 p2, n4, p3, n5, p15, p16, p17, n17 sd0 sd1 sd2 sd3 sd4 sd5 sd6 sd7 i signal detect - ports 0-7. signal detect input from the fiber transceiver (these inputs are only active for ports operating in fiber mode). logic high = normal operation (the process of searching for receive idles for the purpose of bringing link up is initiated) logic low = link is declared lost 1. type column coding: i = input, o = output, od = open drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull- down. 2. the ip/id resistors are disabled during h/w power-down mode. 3. tie sd[0:7] inputs to gndpecl if unused. table 11. intel ? lxt9785/lxt9785e network interface signal descriptions ? pqfp pin/ball designation symbol type 1 signal description pqfp pbga 107, 108 111, 110 121, 122 125, 124 136, 137 140, 139 150, 151 154, 153 t2, u1, t3, r4, t6, u5, u7, t7, t10, r10, t11, u11, t14,u15, r14, t15 tpfop0, tpfon0 tpfop1, tpfon1 tpfop2, tpfon2 tpfop3, tpfon3 tpfop4, tpfon4 tpfop5, tpfon5 tpfop6, tpfon6 tpfop7, tpfon7 ao/ai twisted-pair/fiber outputs 2 , positive & negative, ports 0-7. during 100base-tx or 10base-t operation, tpfo pins drive 802.3 compliant pulses onto the line. during 100base-fx operation, tpfo pins produce differential lvpecl outputs for fiber transceivers. 104, 105 115, 114 118, 119 129, 128 132, 133 143, 142 146, 147 157, 156 r2, t1, u3, t4, r6, t5, t8, r8, t9, u9, u13, t12, r12, t13, r16, t16 tpfip0, tpfin0 tpfip1, tpfin1 tpfip2, tpfin2 tpfip3, tpfin3 tpfip4, tpfin4 tpfip5, tpfin5 tpfip6, tpfin6 tpfip7, tpfin7 ai/ao twisted-pair/fiber inputs 3 , positive & negative, ports 0-7. during 100base-tx or 10base-t operation, tpfi pins receive differential 100base-tx or 10base-t signals from the line. during 100base-fx operation, tpfi pins receive differential lvpecl inputs from fiber transceivers. 1. type column coding: ai = analog input, ao = analog output. 2. switched to inputs (see tpfip/n description) when not in fiber mode and mdix is not active [that is, twisted-pair, non-crossover mdi mode]. 3. switched to outputs (see tpfop/n description) when not in fiber mode and mdix is not active [that is, twisted-pair, non-crossover mdi mode].
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 43 document number: 249241 revision number: 007 revision date: august 28, 2003 table 12. intel ? lxt9785/lxt9785e jtag test signal descriptions ? pqfp pin/ball designation symbol type 1 signal description 2,3 pqfp pbga 167 n14 tdi i, st, ip test data input. test data sampled with respect to the rising edge of tck. 168 n15 tdo o, ts test data output. test data driven with respect to the falling edge of tck. 169 n16 tms i, st, ip test mode select. 170 m16 tck i, st, id test clock. clock input for jtag test. 171 m17 trst i, st, ip test reset. reset input for jtag test. 1. type column coding: i = input, o = output, od = open drain, ts = three-state-able output, smt = schmitt triggered input, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull- down. 2. the ip/id resistors are disabled during h/w power-do wn mode. if a pin is an output or an i/o, the ip/id resistors are also disabled when the output is enabled. 3. tdo output is three-stated in h/w power-down mode and during h/w reset. table 13. intel ? lxt9785/lxt9785e miscellaneous signal descriptions ? pqfp (sheet 1 of 4) pin/ball designation symbol type 1 signal description 2 pqfp pbga 94 93 n3, m4 txslew_0 txslew_1 i, st, id tx output slew controls 0 and 1 defaults. these pins are read at startup or reset. their value at that time is used to set the default state of register bits 27.11:10 for all ports. these register bits can be read and overwritten after startup / reset. these pins select the tx output slew rate for all ports (rise and fall time) as follows: txslew_1 txslew_0 slew rate (rise and fall time) 0 0 3.3 ns 0 1 3.6 ns 1 0 3.9 ns 1 1 4.2 ns 1. type column coding: i = input, o = output, od = open drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull-down. 2. the ip/id resistors are disabled during hardware power-down mode.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 44 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 50 d5 pause i, id, st pause default. this pin is read at startup or reset. its value at that time is used to set the default state of register bit 4.10 for all ports. this register bi t can be read and overwritten after startup / reset. when high, the lxt9785/ 9785e advertises pause capabilities on all ports during auto-negotiation. this pin is shared with rmii- rxer1. an external pull- up resistor (see applications section for value) can be used to set pause active while rxer1 is three-stated during h/w reset. if no pull-up is used, the default pause state is set inactive via the internal pull-down resistor. 174 l14 pwrdwn i, st, id power-down. when high, forces the lxt9785/9785e into global power-down mode. pin is not on jtag chain. 175 m15 reset i, st, ip reset. this active low input is ored with the control register reset register bit 0.15. when held low, all outputs are forced to inactive state. pin is not on jtag chain. 88 89 90 91 92 l4, m2, m3, n1, n2 add_4 add_3 add_2 add_1 add_0 i, st, id address <4:0>. sets base address. each port adds its port number (starting with 0) to this address to determine its phy address. port 0 address = base port 1 address = base + 1 port 2 address = base + 2 port 3 address = base + 3 port 4 address = base + 4 port 5 address = base + 5 port 6 address = base + 6 port 7 address = base + 7 178 177 l17, l16 modesel_1 modesel_0 i, st, id mode select[1:0]. 00 = rmii 01 = smii 10 = ss-smii 11 = reserved all ports are configured the same. interfaces cannot be mixed and must be all rmii, smii, or ss-smii. 176 l15 section i, st, id sectionalization select. this pin selects sectionalization into separate ports. 0 = 1x8 ports, 1 = 2x4 ports table 13. intel ? lxt9785/lxt9785e miscellaneous signal descriptions ? pqfp (sheet 2 of 4) pin/ball designation symbol type 1 signal description 2 pqfp pbga 1. type column coding: i = input, o = output, od = open drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull-down. 2. the ip/id resistors are disabled during hardware power-down mode.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 45 document number: 249241 revision number: 007 revision date: august 28, 2003 83 k1 amdix_en i, st, ip auto mdix enable default. this pin is read at startup or reset. its value at that time is used to set the default state of register bit 27.9 for all ports. these register bits can be read and overwritten after startup / reset. refer to table 40 on page 119 . when active (high), automatic mdi crossover (mdix) (regardless of segmentation) is selected for all ports. when inactive (low) mdix is selected according to the mdix pin. 59 d2 mdix i, id, st mdix select default. this pin is read at startup or reset. its value at that time is used to set the default state of register bit 27.8 for all ports. these register bits can be read and overwritten after startup / reset. refer to table 40, ?intel? lxt9785/lxt9785e mdix selection? on page 119 . when amdix_en is active this pin is ignored. when amdix_en is inactive, all ports are forced to the mdi or the mdix function regardless of segmentation. if this pin is active (high), mdi crossover (mdix) is selected. if this pin is inactive, non-crossover mdi mode is set. this pin is shared with rmii-rxer0. an external pull- up resistor (see applications section for value) can be used to set mdix active while rxer0 is three-stated during h/w reset. if no pull-up is used, the default mdix state is set inactive via the internal pull-down resistor. do not tie this pin directly to vccio (vs. using a pull-up) in non-rmii modes. 85 86 87 l2, l3, m1 cfg_3 cfg_2 cfg_1 i, st, id global port configuration defaults 1-3. these pins are read at startup or reset. their value at that time is used to set the default state of register bits shown in table 42, ?intel? lxt9785/9785e global hardware configuration settings? on page 129 for all ports. these register bits can be read and overwritten after startup / reset. when operating in hardware control mode, these pins provide configuration control options for all the ports (refer to page 129 for details). 173 m14 g_fx/tp i, st, id global fx/tp enable default. this pin is read at startup or reset. its value at that time is used to set the default state of register bit 16.0 for all ports. these register bits can be read and overwritten after startup / reset. refer to table 92, ?port configuration register (address 16, hex 10)? on page 207 . this input selects whether al l the ports are defaulted to tp vs. fx mode. table 13. intel ? lxt9785/lxt9785e miscellaneous signal descriptions ? pqfp (sheet 3 of 4) pin/ball designation symbol type 1 signal description 2 pqfp pbga 1. type column coding: i = input, o = output, od = open drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull-down. 2. the ip/id resistors are disabled during hardware power-down mode.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 46 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 11 20 a15 a12 fifosel1 fifosel0 i, id, st fifo select <1:0>. these pins are read at startup or reset. their value at that time is used to set the default state of register bits 18.15:14 for all ports. these register bits can be read and overwritten after startup/reset. these pins are shared with rmii-rxer<5:4>. an external pull-up resistor (s ee applications section for value) can be used to set fifo select<1:0> to active while rxer<5:4> are three-stated during hardware reset. if no pull-up is used, the default fifo select state is set via the internal pull-down resistors. see table 17, ?intel? lxt9785/lxt9785e receive fifo depth considerations? on page 50 . 40 d7 preasel i, id, st preamble select. this pin is read at startup or reset. its value at that time is used to set the default state of register bit 16.5 for all ports. this register bi t can be read and overwritten after startup/reset. this pin is shared with rmii- rxer2. an external pull- up resistor (see applications section for value) can be used to set preamble select to active while rxer2 is three-stated during hardware reset. if no pull-up is used, the default preamble select state is set via the internal pull-down resistors. note: preamble select has no effect in 100 mbps operation. 2 a17 linkhold id linkhold defaul t. this pin is read at startup or reset. its value at that time is used to set the default state of register bit 0.11 fo r all ports. this register bit can be read and overwritten after startup / reset. when high, the lxt9785/9785e powers down all ports. this pin is shared with rmii- rxer6. an external pull- up resistor (see applications section for value) can be used to set linkhold active while rxer6 is tri-stated during h/w reset. if no pull-up is used, the default linkhold state is set inactive via the internal pull- down resistor. table 13. intel ? lxt9785/lxt9785e miscellaneous signal descriptions ? pqfp (sheet 4 of 4) pin/ball designation symbol type 1 signal description 2 pqfp pbga 1. type column coding: i = input, o = output, od = open drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull-down. 2. the ip/id resistors are disabled during hardware power-down mode.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 47 document number: 249241 revision number: 007 revision date: august 28, 2003 table 14. intel ? lxt9785/lxt9785e led signal descriptions ? pqfp (sheet 1 of 2) pin/ball designation symbol type 1 signal description 2,3 pqfp pbga 82 81 80 k3, k2, j1 led0_1 led0_2 led0_3 od, ts, sl, ip port 0 led drivers 1-3. these pins drive led indicators for port 0. each led can display one of several available status conditions as selected by the led configuration register (refer to table 96, ?led configuration register (address 20, hex 14)? on page 213 for details). 77 76 75 j4, j3, h1 led1_1 led1_2 led1_3 od, ts, sl, ip port 1 led drivers 1-3. these pins drive led indicators for port 1. each led can display one of several available status conditions as selected by the led configuration register (refer to table 96, ?led configuration register (address 20, hex 14)? on page 213 for details). 73 72 71 h2, h3, g1 led2_1 led2_2 led2_3 od, ts, sl, ip port 2 led drivers 1-3. these pins drive led indicators for port 2. each led can display one of several available status conditions as selected by the led configuration register (refer to table 96, ?led configuration register (address 20, hex 14)? on page 213 for details). 70 69 68 f2, g3, g4 led3_1 led3_2 led3_3 od, ts, sl, ip port 3 led drivers 1-3. these pins drive led indicators for port 3. each led can display one of several available status conditions as selected by the led configuration register (refer to table 96, ?led configuration register (address 20, hex 14)? on page 213 for details). 180 181 182 k16, k17, j17 led4_1 led4_2 led4_3 od, ts, sl, ip port 4 led drivers 1-3. these pins drive led indicators for port 4. each led can display one of several available status conditions as selected by the led configuration register (refer to table 96, ?led configuration register (address 20, hex 14)? on page 213 for details). 1. type column coding: i = input, o = output, od = o pen drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull- down. 2. the ip/id resistors are disabled during h/w power-do wn mode. if a pin is an output or an i/o, the ip/id resistors are also disabled when the output is enabled. 3. the led outputs are three-stated in h/w power-down mode and during h/w reset. 4.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 48 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 185 186 187 j15, j16, h17 led5_1 led5_2 led5_3 od, ts, sl, ip port 5 led drivers 1-3. these pins drive led indicators for port 5. each led can display one of several av ailable status conditions as selected by the led configuration register (refer to table 96, ?led configuration register (address 20, hex 14)? on page 213 for details). 189 190 191 h15, h16, g17 led6_1 led6_2 led6_3 od, ts, sl, ip port 6 led drivers 1-3. these pins drive led indicators for port 6. each led can display one of several av ailable status conditions as selected by the led configuration register (refer to table 96, ?led configuration register (address 20, hex 14)? on page 213 for details). 192 193 194 g15, f17, f16 led7_1 led7_2 led7_3 od, ts, sl, ip port 7 led drivers 1-3. these pins drive led indicators for port 7. each led can display one of several av ailable status conditions as selected by the led configuration register (refer to table 96, ?led configuration register (address 20, hex 14)? on page 213 for details). table 15. intel ? lxt9785/lxt9785e power supply signal d escriptions ? pqfp (sheet 1 of 2) pin/ball designation symbol type signal description pqfp pbga 65, 78, 184, 196 g13, j14, f5, j5 vccd - digital power supply - core. +2.5 v supply for core digital circuits. 18, 29, 47, 56, 208 a2, a8, c1, c11, d14 vccio - digital power supply - i/o ring. +2.5/3.3 v supply for digital i/o circuits. the digital input circuits running off of this rail, having a ttl-level threshold and over-voltage protection, may be interfaced with 3.3/5.0 v, when the io supply is 3.3 v, and 2.5/3.3/5.0 v when 2.5 v. 98, 164 l13, l5 vccpecl - digital power supply - pecl signal detect inputs. +2.5/3.3 v supply for pecl signal detect input circuits. if fiber mode is not used, tie these pins to gndpecl to save power. 103, 116, 117, 130, 131, 144, 145, 158 n13, p4, p7, p8, p9, p10, p11, p12 vccr - analog power supply - receive. +2.5 v supply for all ana log receive circuits. 1. type column coding: i = input, o = output, od = open drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull- down. table 14. intel ? lxt9785/lxt9785e led signal descriptions ? pqfp (sheet 2 of 2) pin/ball designation symbol type 1 signal description 2,3 pqfp pbga 1. type column coding: i = input, o = output, od = open drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull- down. 2. the ip/id resistors are disabled during h/w power-down mode. if a pin is an output or an i/o, the ip/id resistors are also disabled when the output is enabled. 3. the led outputs are three-stated in h/w power-down mode and during h/w reset. 4.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 49 document number: 249241 revision number: 007 revision date: august 28, 2003 109, 123, 138, 152 n6, n7, n9, n11, n12 vcct - analog power supply - transmit. +2.5 v supply for all analog transmit circuits. 66, 79, 183, 195 a1, a9, b3, b7, c5, c13, c17, d1, d3, d6, d10, d15, e5, e7, e9, e11, e13, e17, f13, h8, h9, h10, j8, j9, j10, k8, k9, k10 gndd - digital ground. ground return for core digital supplies (vccd). all ground pins can be tied together using a single ground plane. 9, 19, 30, 38, 48, 57, 74, 188, 199, 207 gndio - digital gnd - i/o ring. ground return for digital i/o circuits (vccio). 99, 163 m5, m13 gndpecl - digital gnd - pecl signal detect inputs. ground return for pecl signal detect input circuits. 106, 112, 120, 126, 135, 141, 149, 155 p5, p6, p13, r7, r9, r11, r13, u8 gndr - analog ground - receive. ground return for receive analog supply. all ground pins can be tied together using a single ground plane. 113, 127, 134, 148 p14, r1, r3, r5, r15, r17, t17, u2, u4, u6, u10, u12, u14, u16, u17 gndt - analog ground - transmit. ground return for transmit analog supply. all ground pins can be tied together using a single ground plane. 179 k14 sgnd - substrate ground. ground for chip substrate. all ground pins can be tied together using a single ground plane. table 15. intel ? lxt9785/lxt9785e power supply signal descriptions ? pqfp (sheet 2 of 2) pin/ball designation symbol type signal description pqfp pbga 1. type column coding: i = input, o = output, od = o pen drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull- down.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 50 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 table 16. intel ? lxt9785/lxt9785e unused/reserved pins ? pqfp pin/ball designation symbol type 1 signal description pqfp pbga n/c f15, g2, g5, g14, g16, h4, h14, j2, j13, k4, k15 n/c ? no connection. 1. type column coding: i = input, o = output, od = open drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull- down. 2. table 17. intel ? lxt9785/lxt9785e receive fifo depth considerations fifosel1 fifosel0 register 18.15 value register 18.14 value 00 1 0 01 1 1 10 0 0 11 0 1
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 51 document number: 249241 revision number: 007 revision date: august 28, 2003 3.3 bga23 ball assignments the following sections provide bga23 ball location and signal description information for rmii, smii, and ss-smii: ? table 3.3.1 ?rmii bga23 ball list? on page 52 ? table 3.3.2 ?smii bga23 ball list? on page 62 ? table 3.3.3 ?ss-smii bga23 ball list? on page 72 ? table 3.4 ?bga23 signal descriptions? on page 82 figure 5 illustrates the lxt9785/lxt9785e 241-ball bga23 ball locations for rmii, smii, and ss-smii. figure 5. intel? lxt9785/lxt9785e 241-ball bga23 assignments (top view) b1498-01 a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 b c d e f g h j k l m n p r t u a b c d e f g h j k l m n p r t u = no ball u6 u5 u4 u3 u2 u1 t6 t5 t4 t3 t2 t1 r6 r5 r4 r3 r2 r1 p6 p5 p4 p3 p2 p1 n6 n5 n4 n3 n2 n1 m6 m5 m4 m3 m2 m1 l6 l5 l4 l3 l2 l1 k6 k5 k4 k3 k2 k1 j6 j5 j4 j3 j2 j1 h6 h5 h4 h3 h2 h1 g6 g5 g4 g3 g2 g1 f17 f16 f15 f14 f13 f12 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 e17 e16 e15 e14 e13 e12 e11 e10 e9 e8 e7 e6 e5 e4 e3 e2 e1 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 c17 c16 c15 c14 c13 c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b1 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 b2 g7 g8 g9 g10 g11 g12 g13 g14 g15 g16 g17 h7 h8 h9 h10 h11 h12 h13 h14 h15 h16 h17 j7 k7 l7 m7 j8 k8 l8 m8 j9 k9 l9 m9 j10 k10 l10 m10 j11 k11 l11 m11 j12 k12 l12 m12 j13 k13 l13 m13 j14 k14 l14 m14 j15 k15 l15 m15 j16 k16 l16 m16 j17 k17 l17 m17 n7 p7 r7 t7 u7 n8 p8 r8 t8 u8 n9 p9 r9 t9 u9 n10 p10 r10 t10 u10 n11 p11 r11 t11 u11 n12 p12 r12 t12 u12 n13 p13 r13 t13 u13 n14 p14 r14 t14 u14 n15 p15 r15 t15 u15 n16 p16 r16 t16 u16 n17 p17 r17 t17 u17
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 52 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 3.3.1 rmii bga23 ball list the following tables provide the rmii bga23 ball locations and signal names arranged in alphanumeric order as follows: ? table 18 ?intel? lxt9785/lxt9785e rmii bga23 ball list in alphanumeric order by signal name? ? table 19 ?intel? lxt9785/lxt9785e rmii bga23 ball list in alphanumeric order by ball location? on page 57 table 18. intel? lxt9785/lxt9785e rmii bga23 ball list in alphanumeric order by signal name signal ball type 1 reference for full description add_0 n2 i, st, id table 32 (page 90) add_1 n1 i, st, id table 32 (page 90) add_2 m3 i, st, id table 32 (page 90) add_3 m2 i, st, id table 32 (page 90) add_4 l4 i, st, id table 32 (page 90) amdix_en k1 i, st, ip table 32 (page 90) cfg_1 m1 i, st, id table 32 (page 90) cfg_2 l3 i, st, id table 32 (page 90) cfg_3 l2 i, st, id table 32 (page 90) crs_dv0 e4 o, ts, sl table 24 (page 82) crs_dv1 c4 o, ts, sl table 24 (page 82) crs_dv2 a5 o, ts, sl table 24 (page 82) crs_dv3 b8 o, ts, sl table 24 (page 82) crs_dv4 b12 o, ts, sl table 24 (page 82) crs_dv5 d12 o, ts, sl table 24 (page 82) crs_dv6 b16 o, ts, sl table 24 (page 82) crs_dv7 e15 o, ts, sl table 24 (page 82) g_fx/tp m14 i, st, id table 32 (page 90) gndd a1 ? table 34 (page 95) gndd a9 ? table 34 (page 95) gndd b3 ? table 34 (page 95) gndd b7 ? table 34 (page 95) gndd c5 ? table 34 (page 95) gndd c13 ? table 34 (page 95) gndd c17 ? table 34 (page 95) gndd d1 ? table 34 (page 95) gndd d3 ? table 34 (page 95) gndd d6 ? table 34 (page 95) gndd d10 ? table 34 (page 95) gndd d15 ? table 34 (page 95) gndd e5 ? table 34 (page 95) gndd e7 ? table 34 (page 95) gndd e9 ? table 34 (page 95) gndd e11 ? table 34 (page 95) gndd e13 ? table 34 (page 95) gndd e17 ? table 34 (page 95) gndd f13 ? table 34 (page 95) gndd h8 ? table 34 (page 95) gndd h9 ? table 34 (page 95) gndd h10 ? table 34 (page 95) gndd j8 ? table 34 (page 95) gndd j9 ? table 34 (page 95) gndd j10 ? table 34 (page 95) gndd k8 ? table 34 (page 95) gndd k9 ? table 34 (page 95) gndd k10 ? table 34 (page 95) gndpecl m5 ? table 34 (page 95) gndpecl m13 ? table 34 (page 95) gndr p5 ? table 34 (page 95) gndr p6 ? table 34 (page 95) gndr p13 ? table 34 (page 95) gndr r7 ? table 34 (page 95) gndr r9 ? table 34 (page 95) gndr r11 ? table 34 (page 95) gndr r13 ? table 34 (page 95) gndr u8 ? table 34 (page 95) signal ball type 1 reference for full description
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 53 document number: 249241 revision number: 007 revision date: august 28, 2003 gndt p14 ? table 34 (page 95) gndt r1 ? table 34 (page 95) gndt r3 ? table 34 (page 95) gndt r5 ? table 34 (page 95) gndt r15 ? table 34 (page 95) gndt r17 ? table 34 (page 95) gndt t17 ? table 34 (page 95) gndt u2 ? table 34 (page 95) gndt u4 ? table 34 (page 95) gndt u6 ? table 34 (page 95) gndt u10 ? table 34 (page 95) gndt u12 ? table 34 (page 95) gndt u14 ? table 34 (page 95) gndt u16 ? table 34 (page 95) gndt u17 ? table 34 (page 95) led0_1 k3 od, ts, sl, ip table 33 (page 94) led0_2 k2 od, ts, sl, ip table 33 (page 94) led0_3 j1 od, ts, sl, ip table 33 (page 94) led1_1 j4 od, ts, sl, ip table 33 (page 94) led1_2 j3 od, ts, sl, ip table 33 (page 94) led1_3 h1 od, ts, sl, ip table 33 (page 94) led2_1 h2 od, ts, sl, ip table 33 (page 94) led2_2 h3 od, ts, sl, ip table 33 (page 94) led2_3 g1 od, ts, sl, ip table 33 (page 94) led3_1 f2 od, ts, sl, ip table 33 (page 94) led3_2 g3 od, ts, sl, ip table 33 (page 94) led3_3 g4 od, ts, so, ip table 33 (page 94) led4_1 k16 od, ts, sl, ip table 33 (page 94) led4_2 k17 od, ts, sl, ip table 33 (page 94) signal ball type 1 reference for full description led4_3 j17 od, ts, sl, ip table 33 (page 94) led5_1 j15 od, ts, sl, ip table 33 (page 94) led5_2 j16 od, ts, sl, ip table 33 (page 94) led5_3 h17 od, ts, sl, ip table 33 (page 94) led6_1 h15 od, ts, sl, ip table 33 (page 94) led6_2 h16 od, ts, sl, ip table 33 (page 94) led6_3 g17 od, ts, sl, ip table 33 (page 94) led7_1 g15 od, ts, sl, ip table 33 (page 94) led7_2 f17 od, ts, sl, ip table 33 (page 94) led7_3 f16 od, ts, sl, ip table 33 (page 94) mdc0 e1 i, st, id table 28 (page 87) mdc1 b10 i, st, id table 28 (page 87) mddis l1 i, st, id table 28 (page 87) mdint0 f1 od, ts, sl, ip table 28 (page 87) mdint1 c9 od, ts, sl, ip table 28 (page 87) mdio0 f3 i/o, ts, sl, ip table 28 (page 87) mdio1 a10 i/o, ts, sl, ip table 28 (page 87) modesel0 l16 i, st, id table 32 (page 90) modesel1 l17 i, st, id table 32 (page 90) n/c f15 ? table 35 (page 97) n/c g2 ? table 35 (page 97) n/c g5 ? table 35 (page 97) n/c g14 ? table 35 (page 97) n/c g16 ? table 35 (page 97) n/c h4 ? table 35 (page 97) n/c h14 ? table 35 (page 97) n/c j2 ? table 35 (page 97) n/c j13 ? table 35 (page 97) n/c k4 ? table 35 (page 97) n/c k15 ? table 35 (page 97) signal ball type 1 reference for full description
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 54 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 no ball f6 ? ? no ball f7 ? ? no ball f8 ? ? no ball e8 ? ? no ball e10 no ball f9 ? ? no ball f10 ? ? no ball f11 ? ? no ball f12 ? ? no ball g6 ? ? no ball g7 ? ? no ball g8 ? ? no ball g9 ? ? no ball g10 ? ? no ball g11 ? ? no ball g12 ? ? no ball h5 ? ? no ball h6 ? ? no ball h7 ? ? no ball h11 ? ? no ball h12 ? ? no ball h13 ? ? no ball j6 ? ? no ball j7 ? ? no ball j11 ? ? no ball j12 ? ? no ball k5 ? ? no ball k6 ? ? no ball k7 ? ? no ball k11 ? ? no ball k12 ? ? no ball k13 ? ? no ball l6 ? ? no ball l7 ? ? no ball l8 ? ? no ball l9 ? ? no ball l10 ? ? no ball l11 ? ? signal ball type 1 reference for full description no ball l11 ? ? no ball m6 ? ? no ball m7 ? ? no ball m8 ? ? no ball m9 ? ? no ball m10 ? ? no ball m11 ? ? no ball m12 ? ? no ball n8 ? ? no ball n10 ? ? pwrdwn l14 i, st, id table 32 (page 90) refclk0 e6 i table 24 (page 82) refclk1 e12 i table 24 (page 82) reset m15 i, st, ip table 32 (page 90) rxdata0_0 c2 o, ts table 24 (page 82) rxdata0_1 b1 o, ts, id table 24 (page 82) rxdata1_0 a3 o, ts table 24 (page 82) rxdata1_1 b4 o, ts, id table 24 (page 82) rxdata2_0 b6 o, ts table 24 (page 82) rxdata2_1 c7 o, ts, id table 24 (page 82) rxdata3_0 d9 o, ts table 24 (page 82) rxdata3_1 b9 o, ts, id table 24 (page 82) rxdata4_0 a13 o, ts table 24 (page 82) rxdata4_1 c12 o, ts,id table 24 (page 82) rxdata5_0 b14 o, ts table 24 (page 82) rxdata5_1 b15 o, ts, id table 24 (page 82) rxdata6_0 c15 o, ts table 24 (page 82) rxdata6_1 b17 o, ts, id table 24 (page 82) rxdata7_0 e16 o, ts table 24 (page 82) rxdata7_1 f14 o, ts, id table 24 (page 82) rxer0 (mdix) d2 o, ts, sl, id, i, st table 32 (page 90) rxer1 (pause) d5 o, ts, sl, id, i, st table 32 (page 90) rxer2 (preasel) d7 o, ts, sl, id, i, st table 24 (page 82) rxer3 c8 o, ts, sl, id table 24 (page 82) rxer4 (fifosel0) a12 o, ts, sl, id, i, st table 24 (page 82) signal ball type 1 reference for full description
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 55 document number: 249241 revision number: 007 revision date: august 28, 2003 rxer5 (fifosel1) a15 o, ts, sl, id, i, st table 24 (page 82) rxer6link hold a17 o, ts, sl, id table 24 (page 82) rxer7 d17 o, ts, sl, id table 24 (page 82) sd_2p5v p1 i, st, id table 29 (page 88) sd0 p2 i table 29 (page 88) sd1 n4 i table 29 (page 88) sd2 p3 i table 29 (page 88) sd3 n5 i table 29 (page 88) sd4 p15 i table 29 (page 88) sd5 p16 i table 29 (page 88) sd6 p17 i table 29 (page 88) sd7 n17 i table 29 (page 88) section l15 i, st, id table 32 (page 90) sgnd k14 ? table 34 (page 95) tck m16 i, st, id table 31 (page 89) tdi n14 i, st, ip table 31 (page 89) tdo n15 o, ts table 31 (page 89) tms n16 i, st, ip table 31 (page 89) tpfin0 t1 ao/ai table 30 (page 88) tpfin1 t4 ao/ai table 30 (page 88) tpfin2 t5 ao/ai table 30 (page 88) tpfin3 r8 ao/ai table 30 (page 88) tpfin4 u9 ao/ai table 30 (page 88) tpfin5 t12 ao/ai table 30 (page 88) tpfin6 t13 ao/ai table 30 (page 88) tpfin7 t16 ao/ai table 30 (page 88) tpfip0 r2 ao/ai table 30 (page 88) tpfip1 u3 ao/ai table 30 (page 88) tpfip2 r6 ao/ai table 30 (page 88) tpfip3 t8 ao/ai table 30 (page 88) tpfip4 t9 ao/ai table 30 (page 88) tpfip5 u13 ao/ai table 30 (page 88) tpfip6 r12 ao/ai table 30 (page 88) tpfip7 r16 ao/ai table 30 (page 88) tpfon0 u1 ao/ai table 30 (page 88) tpfon1 r4 ao/ai table 30 (page 88) signal ball type 1 reference for full description tpfon2 u5 ao/ai table 30 (page 88) tpfon3 t7 ao/ai table 30 (page 88) tpfon4 r10 ao/ai table 30 (page 88) tpfon5 u11 ao/ai table 30 (page 88) tpfon6 u15 ao/ai table 30 (page 88) tpfon7 t15 ao/ai table 30 (page 88) tpfop0 t2 ao/ai table 30 (page 88) tpfop1 t3 ao/ai table 30 (page 88) tpfop2 t6 ao/ai table 30 (page 88) tpfop3 u7 ao/ai table 30 (page 88) tpfop4 t10 ao/ai table 30 (page 88) tpfop5 t11 ao/ai table 30 (page 88) tpfop6 t14 ao/ai table 30 (page 88) tpfop7 r14 ao/ai table 30 (page 88) trst m17 i, st, ip table 31 (page 89) txdata0_0 e2 i, id table 24 (page 82) txdata0_1 f4 i, id table 24 (page 82) txdata1_0 c3 i, id table 24 (page 82) txdata1_1 d4 i, id table 24 (page 82) txdata2_0 b5 i, id table 24 (page 82) txdata2_1 a4 i, id table 24 (page 82) txdata3_0 d8 i, id table 24 (page 82) txdata3_1 a6 i, id table 24 (page 82) txdata4_0 a11 i, id table 24 (page 82) txdata4_1 c10 i, id table 24 (page 82) txdata5_0 b13 i, id table 24 (page 82) txdata5_1 d11 i, id table 24 (page 82) txdata6_0 d13 i, id table 24 (page 82) txdata6_1 a16 i, id table 24 (page 82) txdata7_0 e14 i, id table 24 (page 82) txdata7_1 c16 i, id table 24 (page 82) txen0 e3 i, id table 24 (page 82) txen1 b2 i, id table 24 (page 82) txen2 c6 i, id table 24 (page 82) txen3 a7 i, id table 24 (page 82) txen4 b11 i, id table 24 (page 82) txen5 a14 i, id table 24 (page 82) txen6 c14 i, id table 24 (page 82) signal ball type 1 reference for full description
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 56 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 txen7 d16 i, id table 24 (page 82) txslew_0 n3 i, st, id table 32 (page 90) txslew_1 m4 i, st, id table 32 (page 90) vccd f5 ? table 34 (page 95) vccd g13 ? table 34 (page 95) vccd j5 ? table 34 (page 95) vccd j14 ? table 34 (page 95) vccio a2 ? table 34 (page 95) vccio a8 ? table 34 (page 95) vccio c1 ? table 34 (page 95) vccio c11 ? table 34 (page 95) vccio d14 ? table 34 (page 95) vccpecl l5 ? table 34 (page 95) vccpecl l13 ? table 34 (page 95) vccr n13 ? table 34 (page 95) vccr p4 ? table 34 (page 95) vccr p7 ? table 34 (page 95) vccr p8 ? table 34 (page 95) vccr p9 ? table 34 (page 95) vccr p10 ? table 34 (page 95) vccr p11 ? table 34 (page 95) vccr p12 ? table 34 (page 95) vcct n6 ? table 34 (page 95) vcct n7 ? table 34 (page 95) vcct n9 ? table 34 (page 95) vcct n11 ? table 34 (page 95) vcct n12 ? table 34 (page 95) signal ball type 1 reference for full description
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 57 document number: 249241 revision number: 007 revision date: august 28, 2003 table 19. intel? lxt9785/lxt9785e rmii bga2 3 ball list in alphanumeric order by ball location ball signal type 1 reference for full description a1 gndd ? table 34 (page 95) a2 vccio ? table 34 (page 95) a3 rxdata1_0 o, ts table 24 (page 82) a4 txdata2_1 i, id table 24 (page 82) a5 crs_dv2 o, ts, sl table 24 (page 82) a6 txdata3_1 i, id table 24 (page 82) a7 txen3 i, id table 24 (page 82) a8 vccio ? table 34 (page 95) a9 gndd ? table 34 (page 95) a10 mdio1 i/o, ts, sl, ip table 28 (page 87) a11 txdata4_0 i, id table 24 (page 82) a12 rxer4 (fifosel0) o, ts, sl, id, i, st table 24 (page 82) a13 rxdata4_0 o, ts table 24 (page 82) a14 txen5 i, id table 24 (page 82) a15 rxer5 (fifosel1) o, ts, sl, id, i, st table 24 (page 82) a16 txdata6_1 i, id table 24 (page 82) a17 rxer6link hold o, ts, sl, id table 24 (page 82) b1 rxdata0_1 o, ts, id table 24 (page 82) b2 txen1 i, id table 24 (page 82) b3 gndd ? table 34 (page 95) b4 rxdata1_1 o, ts, id table 24 (page 82) b5 txdata2_0 i, id table 24 (page 82) b6 rxdata2_0 o, ts table 24 (page 82) b7 gndd ? table 34 (page 95) b8 crs_dv3 o, ts, sl table 24 (page 82) b9 rxdata3_1 o, ts, id table 24 (page 82) b10 mdc1 i, st, id table 28 (page 87) b11 txen4 i, id table 24 (page 82) b12 crs_dv4 o, ts, sl table 24 (page 82) b13 txdata5_0 i, id table 24 (page 82) b14 rxdata5_0 o, ts table 24 (page 82) b15 rxdata5_1 o, ts, id table 24 (page 82) b16 crs_dv6 o, ts, sl table 24 (page 82) b17 rxdata6_1 o, ts, id table 24 (page 82) c1 vccio ? table 34 (page 95) c2 rxdata0_0 o, ts table 24 (page 82) c3 txdata1_0 i, id table 24 (page 82) c4 crs_dv1 o, ts, sl table 24 (page 82) c5 gndd ? table 34 (page 95) c6 txen2 i, id table 24 (page 82) c7 rxdata2_1 o, ts, id table 24 (page 82) c8 rxer3 o, ts, sl, id table 24 (page 82) c9 mdint1 od, ts, sl, ip table 28 (page 87) c10 txdata4_1 i, id table 24 (page 82) c11 vccio ? table 34 (page 95) c12 rxdata4_1 o, ts,id table 24 (page 82) c13 gndd ? table 34 (page 95) c14 txen6 i, id table 24 (page 82) c15 rxdata6_0 o, ts table 24 (page 82) c16 txdata7_1 i, id table 24 (page 82) c17 gndd ? table 34 (page 95) d1 gndd ? table 34 (page 95) d2 rxer0 (mdix) o, ts, sl, id, i, st table 32 (page 90) d3 gndd ? table 34 (page 95) d4 txdata1_1 i, id table 24 (page 82) d5 rxer1 (pause) o, ts, sl, id, i, st table 32 (page 90) d6 gndd ? table 34 (page 95) d7 rxer2 (preasel) o, ts, sl, id, i, st table 24 (page 82) d8 txdata3_0 i, id table 24 (page 82) d9 rxdata3_0 o, ts table 24 (page 82) d10 gndd ? table 34 (page 95) d11 txdata5_1 i, id table 24 (page 82) d12 crs_dv5 o, ts, sl table 24 (page 82) d13 txdata6_0 i, id table 24 (page 82) d14 vccio ? table 34 (page 95) d15 gndd ? table 34 (page 95) ball signal type 1 reference for full description
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 58 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 d16 txen7 i, id table 24 (page 82) d17 rxer7 o, ts, sl, id table 24 (page 82) e1 mdc0 i, st, id table 28 (page 87) e2 txdata0_0 i, id table 24 (page 82) e3 txen0 i, id table 24 (page 82) e4 crs_dv0 o, ts, sl table 24 (page 82) e5 gndd ? table 34 (page 95) e6 refclk0 i table 24 (page 82) e7 gndd ? table 34 (page 95) e8 no ball ? ? e9 gndd ? table 34 (page 95) e10 no ball e11 gndd ? table 34 (page 95) e12 refclk1 i table 24 (page 82) e13 gndd ? table 34 (page 95) e14 txdata7_0 i, id table 24 (page 82) e15 crs_dv7 o, ts, sl table 24 (page 82) e16 rxdata7_0 o, ts table 24 (page 82) e17 gndd ? table 34 (page 95) f1 mdint0 od, ts, sl, ip table 28 (page 87) f2 led3_1 od, ts, sl, ip table 33 (page 94) f3 mdio0 i/o, ts, sl, ip table 28 (page 87) f4 txdata0_1 i, id table 24 (page 82) f5 vccd ? table 34 (page 95) f6 no ball ? ? f7 no ball ? ? f8 no ball ? ? f9 no ball ? ? f10 no ball ? ? f11 no ball ? ? f12 no ball ? ? f13 gndd ? table 34 (page 95) f14 rxdata7_1 o, ts, id table 24 (page 82) f15 n/c ? table 35 (page 97) f16 led7_3 od, ts, sl, ip table 33 (page 94) ball signal type 1 reference for full description f17 led7_2 od, ts, sl, ip table 33 (page 94) g1 led2_3 od, ts, sl, ip table 33 (page 94) g2 n/c ? table 35 (page 97) g3 led3_2 od, ts, sl, ip table 33 (page 94) g4 led3_3 od, ts, so, ip table 33 (page 94) g5 n/c ? table 35 (page 97) g6 no ball ? ? g7 no ball ? ? g8 no ball ? ? g9 no ball ? ? g10 no ball ? ? g11 no ball ? ? g12 no ball ? ? g13 vccd ? table 34 (page 95) g14 n/c ? table 35 (page 97) g15 led7_1 od, ts, sl, ip table 33 (page 94) g16 n/c ? table 35 (page 97) g17 led6_3 od, ts, sl, ip table 33 (page 94) h1 led1_3 od, ts, sl, ip table 33 (page 94) h2 led2_1 od, ts, sl, ip table 33 (page 94) h3 led2_2 od, ts, sl, ip table 33 (page 94) h4 n/c ? table 35 (page 97) h5 no ball ? ? h6 no ball ? ? h7 no ball ? ? h8 gndd ? table 34 (page 95) h9 gndd ? table 34 (page 95) h10 gndd ? table 34 (page 95) h11 no ball ? ? h12 no ball ? ? h13 no ball ? ? h14 n/c ? table 35 (page 97) ball signal type 1 reference for full description
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 59 document number: 249241 revision number: 007 revision date: august 28, 2003 h15 led6_1 od, ts, sl, ip table 33 (page 94) h16 led6_2 od, ts, sl, ip table 33 (page 94) h17 led5_3 od, ts, sl, ip table 33 (page 94) j1 led0_3 od, ts, sl, ip table 33 (page 94) j2 n/c ? table 35 (page 97) j3 led1_2 od, ts, sl, ip table 33 (page 94) j4 led1_1 od, ts, sl, ip table 33 (page 94) j5 vccd ? table 34 (page 95) j6 no ball ? ? j7 no ball ? ? j8 gndd ? table 34 (page 95) j9 gndd ? table 34 (page 95) j10 gndd ? table 34 (page 95) j11 no ball ? ? j12 no ball ? ? j13 n/c ? table 35 (page 97) j14 vccd ? table 34 (page 95) j15 led5_1 od, ts, sl, ip table 33 (page 94) j16 led5_2 od, ts, sl, ip table 33 (page 94) j17 led4_3 od, ts, sl, ip table 33 (page 94) k1 amdix_en i, st, ip table 32 (page 90) k2 led0_2 od, ts, sl, ip table 33 (page 94) k3 led0_1 od, ts, sl, ip table 33 (page 94) k4 n/c ? table 35 (page 97) k5 no ball ? ? k6 no ball ? ? k7 no ball ? ? k8 gndd ? table 34 (page 95) k9 gndd ? table 34 (page 95) k10 gndd ? table 34 (page 95) k11 no ball ? ? ball signal type 1 reference for full description k12 no ball ? ? k13 no ball ? ? k14 sgnd ? table 34 (page 95) k15 n/c ? table 35 (page 97) k16 led4_1 od, ts, sl, ip table 33 (page 94) k17 led4_2 od, ts, sl, ip table 33 (page 94) l1 mddis i, st, id table 28 (page 87) l2 cfg_3 i, st, id table 32 (page 90) l3 cfg_2 i, st, id table 32 (page 90) l4 add_4 i, st, id table 32 (page 90) l5 vccpecl ? table 34 (page 95) l6 no ball ? ? l7 no ball ? ? l8 no ball ? ? l9 no ball ? ? l10 no ball ? ? l11 no ball ? ? l11 no ball ? ? l13 vccpecl ? table 34 (page 95) l14 pwrdwn i, st, id table 32 (page 90) l15 section i, st, id table 32 (page 90) l16 modesel0 i, st, id table 32 (page 90) l17 modesel1 i, st, id table 32 (page 90) m1 cfg_1 i, st, id table 32 (page 90) m2 add_3 i, st, id table 32 (page 90) m3 add_2 i, st, id table 32 (page 90) m4 txslew_1 i, st, id table 32 (page 90) m5 gndpecl ? table 34 (page 95) m6 no ball ? ? m7 no ball ? ? m8 no ball ? ? m9 no ball ? ? m10 no ball ? ? m11 no ball ? ? m12 no ball ? ? m13 gndpecl ? table 34 (page 95) m14 g_fx/tp i, st, id table 32 (page 90) ball signal type 1 reference for full description
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 60 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 m15 reset i, st, ip table 32 (page 90) m16 tck i, st, id table 31 (page 89) m17 trst i, st, ip table 31 (page 89) n1 add_1 i, st, id table 32 (page 90) n2 add_0 i, st, id table 32 (page 90) n3 txslew_0 i, st, id table 32 (page 90) n4 sd1 i table 29 (page 88) n5 sd3 i table 29 (page 88) n6 vcct ? table 34 (page 95) n7 vcct ? table 34 (page 95) n8 no ball ? ? n9 vcct ? table 34 (page 95) n10 no ball ? ? n11 vcct ? table 34 (page 95) n12 vcct ? table 34 (page 95) n13 vccr ? table 34 (page 95) n14 tdi i, st, ip table 31 (page 89) n15 tdo o, ts table 31 (page 89) n16 tms i, st, ip table 31 (page 89) n17 sd7 i table 29 (page 88) p1 sd_2p5v i, st, id table 29 (page 88) p2 sd0 i table 29 (page 88) p3 sd2 i table 29 (page 88) p4 vccr ? table 34 (page 95) p5 gndr ? table 34 (page 95) p6 gndr ? table 34 (page 95) p7 vccr ? table 34 (page 95) p8 vccr ? table 34 (page 95) p9 vccr ? table 34 (page 95) p10 vccr ? table 34 (page 95) p11 vccr ? table 34 (page 95) p12 vccr ? table 34 (page 95) p13 gndr ? table 34 (page 95) p14 gndt ? table 34 (page 95) p15 sd4 i table 29 (page 88) p16 sd5 i table 29 (page 88) p17 sd6 i table 29 (page 88) r1 gndt ? table 34 (page 95) ball signal type 1 reference for full description r2 tpfip0 ao/ai table 30 (page 88) r3 gndt ? table 34 (page 95) r4 tpfon1 ao/ai table 30 (page 88) r5 gndt ? table 34 (page 95) r6 tpfip2 ao/ai table 30 (page 88) r7 gndr ? table 34 (page 95) r8 tpfin3 ao/ai table 30 (page 88) r9 gndr ? table 34 (page 95) r10 tpfon4 ao/ai table 30 (page 88) r11 gndr ? table 34 (page 95) r12 tpfip6 ao/ai table 30 (page 88) r13 gndr ? table 34 (page 95) r14 tpfop7 ao/ai table 30 (page 88) r15 gndt ? table 34 (page 95) r16 tpfip7 ao/ai table 30 (page 88) r17 gndt ? table 34 (page 95) t1 tpfin0 ao/ai table 30 (page 88) t2 tpfop0 ao/ai table 30 (page 88) t3 tpfop1 ao/ai table 30 (page 88) t4 tpfin1 ao/ai table 30 (page 88) t5 tpfin2 ao/ai table 30 (page 88) t6 tpfop2 ao/ai table 30 (page 88) t7 tpfon3 ao/ai table 30 (page 88) t8 tpfip3 ao/ai table 30 (page 88) t9 tpfip4 ao/ai table 30 (page 88) t10 tpfop4 ao/ai table 30 (page 88) t11 tpfop5 ao/ai table 30 (page 88) t12 tpfin5 ao/ai table 30 (page 88) t13 tpfin6 ao/ai table 30 (page 88) t14 tpfop6 ao/ai table 30 (page 88) t15 tpfon7 ao/ai table 30 (page 88) t16 tpfin7 ao/ai table 30 (page 88) t17 gndt ? table 34 (page 95) u1 tpfon0 ao/ai table 30 (page 88) u2 gndt ? table 34 (page 95) u3 tpfip1 ao/ai table 30 (page 88) u4 gndt ? table 34 (page 95) u5 tpfon2 ao/ai table 30 (page 88) ball signal type 1 reference for full description
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 61 document number: 249241 revision number: 007 revision date: august 28, 2003 u6 gndt ? table 34 (page 95) u7 tpfop3 ao/ai table 30 (page 88) u8 gndr ? table 34 (page 95) u9 tpfin4 ao/ai table 30 (page 88) u10 gndt ? table 34 (page 95) u11 tpfon5 ao/ai table 30 (page 88) u12 gndt ? table 34 (page 95) u13 tpfip5 ao/ai table 30 (page 88) u14 gndt ? table 34 (page 95) u15 tpfon6 ao/ai table 30 (page 88) u16 gndt ? table 34 (page 95) u17 gndt ? table 34 (page 95) ball signal type 1 reference for full description
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 62 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 3.3.2 smii bga23 ball list the following tables prov ide the smii ball locations and signa l names arranged in alphanumeric order as follows: ? table 20 ?intel? lxt9785/lxt9785e smii bga23 ball list in alphanumeric order by signal name? ? table 21 ?intel? lxt9785/lxt9785e smii bga23 ball list in alphanumeric order by ball location? on page 67 table 20. intel? lxt9785/lxt9785e smii bga23 ball list in alphanumeric order by signal name signal ball type 1 reference for full description add_0 n2 i, st, id table 32 (page 90) add_1 n1 i, st, id table 32 (page 90) add_2 m3 i, st, id table 32 (page 90) add_3 m2 i, st, id table 32 (page 90) add_4 l4 i, st, id table 32 (page 90) amdix_en k1 i, st, ip table 32 (page 90) cfg_1 m1 i, st, id table 32 (page 90) cfg_2 l3 i, st, id table 32 (page 90) cfg_3 l2 i, st, id table 32 (page 90) crs_dv0 e4 o, ts, sl table 24 (page 82) crs_dv1 c4 o, ts, sl table 24 (page 82) crs_dv2 a5 o, ts, sl table 24 (page 82) crs_dv3 b8 o, ts, sl table 24 (page 82) crs_dv4 b12 o, ts, sl table 24 (page 82) crs_dv5 d12 o, ts, sl table 24 (page 82) crs_dv6 b16 o, ts, sl table 24 (page 82) crs_dv7 e15 o, ts, sl table 24 (page 82) fifosel0 a12 o, ts, sl, id, i, st table 24 (page 82) fifosel1 a15 o, ts, sl, id, i, st table 24 (page 82) g_fx/tp m14 i, st, id table 32 (page 90) gndd a1 ? table 34 (page 95) gndd a9 ? table 34 (page 95) gndd b3 ? table 34 (page 95) gndd b7 ? table 34 (page 95) gndd c5 ? table 34 (page 95) gndd c13 ? table 34 (page 95) gndd c17 ? table 34 (page 95) gndd d1 ? table 34 (page 95) gndd d3 ? table 34 (page 95) gndd d6 ? table 34 (page 95) gndd d10 ? table 34 (page 95) gndd d15 ? table 34 (page 95) gndd e5 ? table 34 (page 95) gndd e7 ? table 34 (page 95) gndd e9 ? table 34 (page 95) gndd e11 ? table 34 (page 95) gndd e13 ? table 34 (page 95) gndd e17 ? table 34 (page 95) gndd f13 ? table 34 (page 95) gndd h8 ? table 34 (page 95) gndd h9 ? table 34 (page 95) gndd h10 ? table 34 (page 95) gndd j8 ? table 34 (page 95) gndd j9 ? table 34 (page 95) gndd j10 ? table 34 (page 95) gndd k8 ? table 34 (page 95) gndd k9 ? table 34 (page 95) gndd k10 ? table 34 (page 95) gndpecl m5 ? table 34 (page 95) gndpecl m13 ? table 34 (page 95) gndr p5 ? table 34 (page 95) gndr p6 ? table 34 (page 95) gndr p13 ? table 34 (page 95) gndr r7 ? table 34 (page 95) gndr r9 ? table 34 (page 95) signal ball type 1 reference for full description
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 63 document number: 249241 revision number: 007 revision date: august 28, 2003 gndr r11 ? table 34 (page 95) gndr r13 ? table 34 (page 95) gndr u8 ? table 34 (page 95) gndt p14 ? table 34 (page 95) gndt r1 ? table 34 (page 95) gndt r3 ? table 34 (page 95) gndt r5 ? table 34 (page 95) gndt r15 ? table 34 (page 95) gndt r17 ? table 34 (page 95) gndt t17 ? table 34 (page 95) gndt u2 ? table 34 (page 95) gndt u4 ? table 34 (page 95) gndt u6 ? table 34 (page 95) gndt u10 ? table 34 (page 95) gndt u12 ? table 34 (page 95) gndt u14 ? table 34 (page 95) gndt u16 ? table 34 (page 95) gndt u17 ? table 34 (page 95) led0_1 k3 od, ts, sl, ip table 33 (page 94) led0_2 k2 od, ts, sl, ip table 33 (page 94) led0_3 j1 od, ts, sl, ip table 33 (page 94) led1_1 j4 od, ts, sl, ip table 33 (page 94) led1_2 j3 od, ts, sl, ip table 33 (page 94) led1_3 h1 od, ts, sl, ip table 33 (page 94) led2_1 h2 od, ts, sl, ip table 33 (page 94) led2_2 h3 od, ts, sl, ip table 33 (page 94) led2_3 g1 od, ts, sl, ip table 33 (page 94) led3_1 f2 od, ts, sl, ip table 33 (page 94) led3_2 g3 od, ts, sl, ip table 33 (page 94) led3_3 g4 od, ts, so, ip table 33 (page 94) signal ball type 1 reference for full description led4_1 k16 od, ts, sl, ip table 33 (page 94) led4_2 k17 od, ts, sl, ip table 33 (page 94) led4_3 j17 od, ts, sl, ip table 33 (page 94) led5_1 j15 od, ts, sl, ip table 33 (page 94) led5_2 j16 od, ts, sl, ip table 33 (page 94) led5_3 h17 od, ts, sl, ip table 33 (page 94) led6_1 h15 od, ts, sl, ip table 33 (page 94) led6_2 h16 od, ts, sl, ip table 33 (page 94) led6_3 g17 od, ts, sl, ip table 33 (page 94) led7_1 g15 od, ts, sl, ip table 33 (page 94) led7_2 f17 od, ts, sl, ip table 33 (page 94) led7_3 f16 od, ts, sl, ip table 33 (page 94) linkhold a17 o, ts, sl, id, i, st table 24 (page 82) mdc0 e1 i, st, id table 28 (page 87) mdc1 b10 i, st, id table 28 (page 87) mddis l1 i, st, id table 28 (page 87) mdint0 f1 od, ts, sl, ip table 28 (page 87) mdint1 c9 od, ts, sl, ip table 28 (page 87) mdio0 f3 i/o, ts, sl, ip table 28 (page 87) mdio1 a10 i/o, ts, sl, ip table 28 (page 87) mdix d2 o, ts, sl, id, i, st table 32 (page 90) modesel0 l16 i, st, id table 32 (page 90) modesel1 l17 i, st, id table 32 (page 90) n/c a4 i, id table 24 (page 82) n/c a7 i, id table 24 (page 82) n/c a14 i, id table 24 (page 82) n/c a16 i, id table 24 (page 82) signal ball type 1 reference for full description
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 64 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 n/c b1 o, ts, id table 24 (page 82) n/c b2 i, id table 24 (page 82) n/c b4 o, ts, id table 24 (page 82) n/c b9 o, ts, id table 24 (page 82) n/c b11 i, id table 24 (page 82) n/c b15 o, ts, id table 24 (page 82) n/c b17 o, ts, id table 24 (page 82) n/c c6 i, id table 24 (page 82) n/c c7 o, ts, id table 24 (page 82) n/c c8 o, ts, sl, id table 24 (page 82) n/c c10 i, id table 24 (page 82) n/c c12 o, ts,id table 24 (page 82) n/c c14 i, id table 24 (page 82) n/c d4 i, id table 24 (page 82) n/c d11 i, id table 24 (page 82) n/c d16 i, id table 24 (page 82) n/c d17 o, ts, sl, id table 24 (page 82) n/c e3 i, id table 24 (page 82) n/c f4 i, id table 24 (page 82) n/c f14 o, ts, id table 24 (page 82) n/c f15 ? table 35 (page 97) n/c g2 ? table 35 (page 97) n/c g5 ? table 35 (page 97) n/c g14 ? table 35 (page 97) n/c g16 ? table 35 (page 97) n/c h4 ? table 35 (page 97) n/c h14 ? table 35 (page 97) n/c j2 ? table 35 (page 97) n/c j13 ? table 35 (page 97) n/c k4 ? table 35 (page 97) n/c k15 ? table 35 (page 97) no ball f6 ? ? no ball f7 ? ? no ball f8 ? ? no ball e8 ? ? no ball e10 no ball f9 ? ? signal ball type 1 reference for full description no ball f10 ? ? no ball f11 ? ? no ball f12 ? ? no ball g6 ? ? no ball g7 ? ? no ball g8 ? ? no ball g9 ? ? no ball g10 ? ? no ball g11 ? ? no ball g12 ? ? no ball h5 ? ? no ball h6 ? ? no ball h7 ? ? no ball h11 ? ? no ball h12 ? ? no ball h13 ? ? no ball j6 ? ? no ball j7 ? ? no ball j11 ? ? no ball j12 ? ? no ball k5 ? ? no ball k6 ? ? no ball k7 ? ? no ball k11 ? ? no ball k12 ? ? no ball k13 ? ? no ball l6 ? ? no ball l7 ? ? no ball l8 ? ? no ball l9 ? ? no ball l10 ? ? no ball l11 ? ? no ball l11 ? ? no ball m6 ? ? no ball m7 ? ? no ball m8 ? ? no ball m9 ? ? no ball m10 ? ? signal ball type 1 reference for full description
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 65 document number: 249241 revision number: 007 revision date: august 28, 2003 no ball m11 ? ? no ball m12 ? ? no ball n8 ? ? no ball n10 ? ? pause d5 o, ts, sl, id, i, st table 32 (page 90) preasel d7 o, ts, sl, id, i, st table 24 (page 82) pwrdwn l14 i, st, id table 32 (page 90) refclk0 e6 i table 24 (page 82) refclk1 e12 i table 24 (page 82) reset m15 i, st, ip table 32 (page 90) rxdata0 c2 o, ts table 24 (page 82) rxdata1 a3 o, ts table 24 (page 82) rxdata2 b6 o, ts table 24 (page 82) rxdata3 d9 o, ts table 24 (page 82) rxdata4 a13 o, ts table 24 (page 82) rxdata5 b14 o, ts table 24 (page 82) rxdata6 c15 o, ts table 24 (page 82) rxdata7 e16 o, ts table 24 (page 82) sd_2p5v p1 i, st, id table 29 (page 88) sd0 p2 i table 29 (page 88) sd1 n4 i table 29 (page 88) sd2 p3 i table 29 (page 88) sd3 n5 i table 29 (page 88) sd4 p15 i table 29 (page 88) sd5 p16 i table 29 (page 88) sd6 p17 i table 29 (page 88) sd7 n17 i table 29 (page 88) section l15 i, st, id table 32 (page 90) sgnd k14 ? table 34 (page 95) sync0 a6 i, id table 24 (page 82) sync1 c16 i, id table 24 (page 82) tck m16 i, st, id table 31 (page 89) tdi n14 i, st, ip table 31 (page 89) tdo n15 o, ts table 31 (page 89) tms n16 i, st, ip table 31 (page 89) tpfin0 t1 ao/ai table 30 (page 88) tpfin1 t4 ao/ai table 30 (page 88) signal ball type 1 reference for full description tpfin2 t5 ao/ai table 30 (page 88) tpfin3 r8 ao/ai table 30 (page 88) tpfin4 u9 ao/ai table 30 (page 88) tpfin5 t12 ao/ai table 30 (page 88) tpfin6 t13 ao/ai table 30 (page 88) tpfin7 t16 ao/ai table 30 (page 88) tpfip0 r2 ao/ai table 30 (page 88) tpfip1 u3 ao/ai table 30 (page 88) tpfip2 r6 ao/ai table 30 (page 88) tpfip3 t8 ao/ai table 30 (page 88) tpfip4 t9 ao/ai table 30 (page 88) tpfip5 u13 ao/ai table 30 (page 88) tpfip6 r12 ao/ai table 30 (page 88) tpfip7 r16 ao/ai table 30 (page 88) tpfon0 u1 ao/ai table 30 (page 88) tpfon1 r4 ao/ai table 30 (page 88) tpfon2 u5 ao/ai table 30 (page 88) tpfon3 t7 ao/ai table 30 (page 88) tpfon4 r10 ao/ai table 30 (page 88) tpfon5 u11 ao/ai table 30 (page 88) tpfon6 u15 ao/ai table 30 (page 88) tpfon7 t15 ao/ai table 30 (page 88) tpfop0 t2 ao/ai table 30 (page 88) tpfop1 t3 ao/ai table 30 (page 88) tpfop2 t6 ao/ai table 30 (page 88) tpfop3 u7 ao/ai table 30 (page 88) tpfop4 t10 ao/ai table 30 (page 88) tpfop5 t11 ao/ai table 30 (page 88) tpfop6 t14 ao/ai table 30 (page 88) tpfop7 r14 ao/ai table 30 (page 88) trst m17 i, st, ip table 31 (page 89) txdata0 e2 i, id table 24 (page 82) txdata1 c3 i, id table 24 (page 82) txdata2 b5 i, id table 24 (page 82) txdata3 d8 i, id table 24 (page 82) txdata4 a11 i, id table 24 (page 82) txdata5 b13 i, id table 24 (page 82) txdata6 d13 i, id table 24 (page 82) signal ball type 1 reference for full description
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 66 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 txdata7 e14 i, id table 24 (page 82) txslew_0 n3 i, st, id table 32 (page 90) txslew_1 m4 i, st, id table 32 (page 90) vccd f5 ? table 34 (page 95) vccd g13 ? table 34 (page 95) vccd j5 ? table 34 (page 95) vccd j14 ? table 34 (page 95) vccio a2 ? table 34 (page 95) vccio a8 ? table 34 (page 95) vccio c1 ? table 34 (page 95) vccio c11 ? table 34 (page 95) vccio d14 ? table 34 (page 95) vccpecl l5 ? table 34 (page 95) vccpecl l13 ? table 34 (page 95) vccr n13 ? table 34 (page 95) vccr p4 ? table 34 (page 95) vccr p7 ? table 34 (page 95) vccr p8 ? table 34 (page 95) vccr p9 ? table 34 (page 95) vccr p10 ? table 34 (page 95) vccr p11 ? table 34 (page 95) vccr p12 ? table 34 (page 95) vcct n6 ? table 34 (page 95) vcct n7 ? table 34 (page 95) vcct n9 ? table 34 (page 95) vcct n11 ? table 34 (page 95) vcct n12 ? table 34 (page 95) signal ball type 1 reference for full description
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 67 document number: 249241 revision number: 007 revision date: august 28, 2003 table 21. intel? lxt9785/lxt9785e smii bga23 ball list in alpha numeric order by ball location ball signal type 1 reference for full description a1 gndd ? table 34 (page 95) a2 vccio ? table 34 (page 95) a3 rxdata1 o, ts table 24 (page 82) a4 n/c i, id table 24 (page 82) a5 crs_dv2 o, ts, sl table 24 (page 82) a6 sync0 i, id table 24 (page 82) a7 n/c i, id table 24 (page 82) a8 vccio ? table 34 (page 95) a9 gndd ? table 34 (page 95) a10 mdio1 i/o, ts, sl, ip table 28 (page 87) a11 txdata4 i, id table 24 (page 82) a12 fifosel0 o, ts, sl, id, i, st table 24 (page 82) a13 rxdata4 o, ts table 24 (page 82) a14 n/c i, id table 24 (page 82) a15 fifosel1 o, ts, sl, id, i, st table 24 (page 82) a16 n/c i, id table 24 (page 82) a17 linkhold o, ts, sl, id table 24 (page 82) b1 n/c o, ts table 24 (page 82) b2 n/c ? table 24 (page 82) b3 gndd ? table 34 (page 95) b4 n/c o, ts, id table 24 (page 82) b5 txdata2 i, id table 24 (page 82) b6 rxdata2 o, ts table 24 (page 82) b7 gndd ? table 34 (page 95) b8 crs_dv3 o, ts, sl table 24 (page 82) b9 n/c o, ts, id table 24 (page 82) b10 mdc1 i, st, id table 28 (page 87) b11 n/c i, id table 24 (page 82) b12 crs_dv4 o, ts, sl table 24 (page 82) b13 txdata5 i, id table 24 (page 82) b14 rxdata5 o, ts table 24 (page 82) b15 n/c o, ts, id table 24 (page 82) b16 crs_dv6 o, ts, sl table 24 (page 82) b17 n/c o, ts, id table 24 (page 82) c1 vccio ? table 34 (page 95) c2 rxdata0 o, ts table 24 (page 82) c3 txdata1 i, id table 24 (page 82) c4 crs_dv1 o, ts, sl table 24 (page 82) c5 gndd ? table 34 (page 95) c6 n/c i, id table 24 (page 82) c7 n/c o, ts, id table 24 (page 82) c8 n/c o, ts, sl, id table 24 (page 82) c9 mdint1 od, ts, sl, ip table 28 (page 87) c10 n/c i, id table 24 (page 82) c11 vccio ? table 34 (page 95) c12 n/c o, ts,id table 24 (page 82) c13 gndd ? table 34 (page 95) c14 n/c i, id table 24 (page 82) c15 rxdata6 o, ts table 24 (page 82) c16 sync1 i, id table 24 (page 82) c17 gndd ? table 34 (page 95) d1 gndd ? table 34 (page 95) d2 mdix o, ts, sl, id, i, st table 32 (page 90) d3 gndd ? table 34 (page 95) d4 n/c i, id table 24 (page 82) d5 pause o, ts, sl, id, i, st table 32 (page 90) d6 gndd ? table 34 (page 95) d7 preasel o, ts, sl, id, i, st table 24 (page 82) d8 txdata3 i, id table 24 (page 82) d9 rxdata3 o, ts table 24 (page 82) d10 gndd ? table 34 (page 95) d11 n/c i, id table 24 (page 82) d12 crs_dv5 o, ts, sl table 24 (page 82) d13 txdata6 i, id table 24 (page 82) d14 vccio ? table 34 (page 95) d15 gndd ? table 34 (page 95) ball signal type 1 reference for full description
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 68 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 d16 n/c i, id table 24 (page 82) d17 n/c o, ts, sl, id table 24 (page 82) e1 mdc0 i, st, id table 28 (page 87) e2 txdata0 i, id table 24 (page 82) e3 n/c i, id table 24 (page 82) e4 crs_dv0 o, ts, sl table 24 (page 82) e5 gndd ? table 34 (page 95) e6 refclk0 i table 24 (page 82) e7 gndd ? table 34 (page 95) e8 no ball ? ? e9 gndd ? table 34 (page 95) e10 no ball e11 gndd ? table 34 (page 95) e12 refclk1 i table 24 (page 82) e13 gndd ? table 34 (page 95) e14 txdata7 i, id table 24 (page 82) e15 crs_dv7 o, ts, sl table 24 (page 82) e16 rxdata7 o, ts table 24 (page 82) e17 gndd ? table 34 (page 95) f1 mdint0 od, ts, sl, ip table 28 (page 87) f2 led3_1 od, ts, sl, ip table 33 (page 94) f3 mdio0 i/o, ts, sl, ip table 28 (page 87) f4 n/c i, id table 24 (page 82) f5 vccd ? table 34 (page 95) f6 no ball ? ? f7 no ball ? ? f8 no ball ? ? f9 no ball ? ? f10 no ball ? ? f11 no ball ? ? f12 no ball ? ? f13 gndd ? table 34 (page 95) f14 n/c o, ts, id table 24 (page 82) f15 n/c ? table 35 (page 97) f16 led7_3 od, ts, sl, ip table 33 (page 94) ball signal type 1 reference for full description f17 led7_2 od, ts, sl, ip table 33 (page 94) g1 led2_3 od, ts, sl, ip table 33 (page 94) g2 n/c ? table 35 (page 97) g3 led3_2 od, ts, sl, ip table 33 (page 94) g4 led3_3 od, ts, so, ip table 33 (page 94) g5 n/c ? table 35 (page 97) g6 no ball ? ? g7 no ball ? ? g8 no ball ? ? g9 no ball ? ? g10 no ball ? ? g11 no ball ? ? g12 no ball ? ? g13 vccd ? table 34 (page 95) g14 n/c ? table 35 (page 97) g15 led7_1 od, ts, sl, ip table 33 (page 94) g16 n/c ? table 35 (page 97) g17 led6_3 od, ts, sl, ip table 33 (page 94) h1 led1_3 od, ts, sl, ip table 33 (page 94) h2 led2_1 od, ts, sl, ip table 33 (page 94) h3 led2_2 od, ts, sl, ip table 33 (page 94) h4 n/c ? table 35 (page 97) h5 no ball ? ? h6 no ball ? ? h7 no ball ? ? h8 gndd ? table 34 (page 95) h9 gndd ? table 34 (page 95) h10 gndd ? table 34 (page 95) h11 no ball ? ? h12 no ball ? ? h13 no ball ? ? h14 n/c ? table 35 (page 97) ball signal type 1 reference for full description
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 69 document number: 249241 revision number: 007 revision date: august 28, 2003 h15 led6_1 od, ts, sl, ip table 33 (page 94) h16 led6_2 od, ts, sl, ip table 33 (page 94) h17 led5_3 od, ts, sl, ip table 33 (page 94) j1 led0_3 od, ts, sl, ip table 33 (page 94) j2 n/c ? table 35 (page 97) j3 led1_2 od, ts, sl, ip table 33 (page 94) j4 led1_1 od, ts, sl, ip table 33 (page 94) j5 vccd ? table 34 (page 95) j6 no ball ? ? j7 no ball ? ? j8 gndd ? table 34 (page 95) j9 gndd ? table 34 (page 95) j10 gndd ? table 34 (page 95) j11 no ball ? ? j12 no ball ? ? j13 n/c ? table 35 (page 97) j14 vccd ? table 34 (page 95) j15 led5_1 od, ts, sl, ip table 33 (page 94) j16 led5_2 od, ts, sl, ip table 33 (page 94) j17 led4_3 od, ts, sl, ip table 33 (page 94) k1 amdix_en i, st, ip table 32 (page 90) k2 led0_2 od, ts, sl, ip table 33 (page 94) k3 led0_1 od, ts, sl, ip table 33 (page 94) k4 n/c ? table 35 (page 97) k5 no ball ? ? k6 no ball ? ? k7 no ball ? ? k8 gndd ? table 34 (page 95) k9 gndd ? table 34 (page 95) k10 gndd ? table 34 (page 95) k11 no ball ? ? ball signal type 1 reference for full description k12 no ball ? ? k13 no ball ? ? k14 sgnd ? table 34 (page 95) k15 n/c ? table 35 (page 97) k16 led4_1 od, ts, sl, ip table 33 (page 94) k17 led4_2 od, ts, sl, ip table 33 (page 94) l1 mddis i, st, id table 28 (page 87) l2 cfg_3 i, st, id table 32 (page 90) l3 cfg_2 i, st, id table 32 (page 90) l4 add_4 i, st, id table 32 (page 90) l5 vccpecl ? table 34 (page 95) l6 no ball ? ? l7 no ball ? ? l8 no ball ? ? l9 no ball ? ? l10 no ball ? ? l11 no ball ? ? l11 no ball ? ? l13 vccpecl ? table 34 (page 95) l14 pwrdwn i, st, id table 32 (page 90) l15 section i, st, id table 32 (page 90) l16 modesel0 i, st, id table 32 (page 90) l17 modesel1 i, st, id table 32 (page 90) m1 cfg_1 i, st, id table 32 (page 90) m2 add_3 i, st, id table 32 (page 90) m3 add_2 i, st, id table 32 (page 90) m4 txslew_1 i, st, id table 32 (page 90) m5 gndpecl ? table 34 (page 95) m6 no ball ? ? m7 no ball ? ? m8 no ball ? ? m9 no ball ? ? m10 no ball ? ? m11 no ball ? ? m12 no ball ? ? m13 gndpecl ? table 34 (page 95) m14 g_fx/tp i, st, id table 32 (page 90) ball signal type 1 reference for full description
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 70 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 m15 reset i, st, ip table 32 (page 90) m16 tck i, st, id table 31 (page 89) m17 trst i, st, ip table 31 (page 89) n1 add_1 i, st, id table 32 (page 90) n2 add_0 i, st, id table 32 (page 90) n3 txslew_0 i, st, id table 32 (page 90) n4 sd1 i table 29 (page 88) n5 sd3 i table 29 (page 88) n6 vcct ? table 34 (page 95) n7 vcct ? table 34 (page 95) n8 no ball ? ? n9 vcct ? table 34 (page 95) n10 no ball ? ? n11 vcct ? table 34 (page 95) n12 vcct ? table 34 (page 95) n13 vccr ? table 34 (page 95) n14 tdi i, st, ip table 31 (page 89) n15 tdo o, ts table 31 (page 89) n16 tms i, st, ip table 31 (page 89) n17 sd7 i table 29 (page 88) p1 sd_2p5v i, st, id table 29 (page 88) p2 sd0 i table 29 (page 88) p3 sd2 i table 29 (page 88) p4 vccr ? table 34 (page 95) p5 gndr ? table 34 (page 95) p6 gndr ? table 34 (page 95) p7 vccr ? table 34 (page 95) p8 vccr ? table 34 (page 95) p9 vccr ? table 34 (page 95) p10 vccr ? table 34 (page 95) p11 vccr ? table 34 (page 95) p12 vccr ? table 34 (page 95) p13 gndr ? table 34 (page 95) p14 gndt ? table 34 (page 95) p15 sd4 i table 29 (page 88) p16 sd5 i table 29 (page 88) p17 sd6 i table 29 (page 88) r1 gndt ? table 34 (page 95) ball signal type 1 reference for full description r2 tpfip0 ao/ai table 30 (page 88) r3 gndt ? table 34 (page 95) r4 tpfon1 ao/ai table 30 (page 88) r5 gndt ? table 34 (page 95) r6 tpfip2 ao/ai table 30 (page 88) r7 gndr ? table 34 (page 95) r8 tpfin3 ao/ai table 30 (page 88) r9 gndr ? table 34 (page 95) r10 tpfon4 ao/ai table 30 (page 88) r11 gndr ? table 34 (page 95) r12 tpfip6 ao/ai table 30 (page 88) r13 gndr ? table 34 (page 95) r14 tpfop7 ao/ai table 30 (page 88) r15 gndt ? table 34 (page 95) r16 tpfip7 ao/ai table 30 (page 88) r17 gndt ? table 34 (page 95) t1 tpfin0 ao/ai table 30 (page 88) t2 tpfop0 ao/ai table 30 (page 88) t3 tpfop1 ao/ai table 30 (page 88) t4 tpfin1 ao/ai table 30 (page 88) t5 tpfin2 ao/ai table 30 (page 88) t6 tpfop2 ao/ai table 30 (page 88) t7 tpfon3 ao/ai table 30 (page 88) t8 tpfip3 ao/ai table 30 (page 88) t9 tpfip4 ao/ai table 30 (page 88) t10 tpfop4 ao/ai table 30 (page 88) t11 tpfop5 ao/ai table 30 (page 88) t12 tpfin5 ao/ai table 30 (page 88) t13 tpfin6 ao/ai table 30 (page 88) t14 tpfop6 ao/ai table 30 (page 88) t15 tpfon7 ao/ai table 30 (page 88) t16 tpfin7 ao/ai table 30 (page 88) t17 gndt ? table 34 (page 95) u1 tpfon0 ao/ai table 30 (page 88) u2 gndt ? table 34 (page 95) u3 tpfip1 ao/ai table 30 (page 88) u4 gndt ? table 34 (page 95) u5 tpfon2 ao/ai table 30 (page 88) ball signal type 1 reference for full description
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 71 document number: 249241 revision number: 007 revision date: august 28, 2003 u6 gndt ? table 34 (page 95) u7 tpfop3 ao/ai table 30 (page 88) u8 gndr ? table 34 (page 95) u9 tpfin4 ao/ai table 30 (page 88) u10 gndt ? table 34 (page 95) u11 tpfon5 ao/ai table 30 (page 88) u12 gndt ? table 34 (page 95) u13 tpfip5 ao/ai table 30 (page 88) u14 gndt ? table 34 (page 95) u15 tpfon6 ao/ai table 30 (page 88) u16 gndt ? table 34 (page 95) u17 gndt ? table 34 (page 95) ball signal type 1 reference for full description
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 72 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 3.3.3 ss-smii bga23 ball list the following tables provide the ss-smii ball locations and signal names arranged in alphanumeric order as follows: ? table 22 ?intel? lxt9785/lxt9785e ss-smii b ga23 ball list in alphanumeric order by signal name? ? table 23 ?intel? lxt9785/lxt9785e ss-smii b ga23 ball list in alphanumeric order by ball location? on page 77 table 22. intel? lxt9785/lxt9785e ss-smii bga23 ball list in alphanumeric order by signal name signal ball type 1 reference for full description add_0 n2 i table 29 (page 88) add_1 n1 i, st, id table 29 (page 88) add_2 m3 ? ? add_3 m2 ? ? add_4 l4 ? ? amdix_en k1 ? ? cfg_1 m1 ? ? cfg_2 l3 ? ? cfg_3 l2 ? ? crs_dv0 e4 od, ts, sl, ip table 33 (page 94) crs_dv1 c4 ? table 34 (page 95) crs_dv2 a5 i, st, id table 32 (page 90) crs_dv3 b8 ? table 34 (page 95) crs_dv4 b12 ? table 34 (page 95) crs_dv5 d12 ? table 34 (page 95) crs_dv6 b16 ? table 34 (page 95) crs_dv7 e15 od, ts, so, ip table 33 (page 94) fifosel0 a12 o, ts, sl, i, st table 24 (page 82) fifosel1 a15 o, ts, sl, i, st table 24 (page 82) g_fx/tp m14 o, ts table 24 (page 82) gndd a1 i, st, id table 32 (page 90) gndd a9 i, st, id table 32 (page 90) gndd b3 ? table 34 (page 95) gndd b7 ? table 34 (page 95) gndd c5 ? table 34 (page 95) gndd c13 ? table 34 (page 95) gndd c17 ? table 34 (page 95) gndd d1 ? table 34 (page 95) gndd d3 ? table 34 (page 95) gndd d6 ? table 34 (page 95) gndd d10 ? table 34 (page 95) gndd d15 ? table 34 (page 95) gndd e5 od, ts, sl, ip table 33 (page 94) gndd e7 od, ts, sl, ip table 33 (page 94) gndd e9 od, ts, sl, ip table 33 (page 94) gndd e11 od, ts, sl, ip table 33 (page 94) gndd e13 od, ts, sl, ip table 33 (page 94) gndd e17 od, ts, sl, ip table 33 (page 94) gndd f13 i, st, id table 28 (page 87) gndd h8 ? table 24 (page 82) gndd h9 i, id table 24 (page 82) gndd h10 i, id table 24 (page 82) gndd j8 ? ? gndd j9 ? ? gndd j10 ? ? gndd k8 ? ? gndd k9 ? ? gndd k10 ? ? gndpecl m5 i, st, id table 32 (page 90) gndpecl m13 o, ts table 24 (page 82) gndr p5 ao/ai table 30 (page 88) signal ball type 1 reference for full description
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 73 document number: 249241 revision number: 007 revision date: august 28, 2003 gndr p6 ao/ai table 30 (page 88) gndr p13 ao/ai table 30 (page 88) gndr r7 ao/ai table 30 (page 88) gndr r9 ao/ai table 30 (page 88) gndr r11 ao/ai table 30 (page 88) gndr r13 ao/ai table 30 (page 88) gndr u8 ? table 34 (page 95) gndt p14 ao/ai table 30 (page 88) gndt r1 ao/ai table 30 (page 88) gndt r3 ao/ai table 30 (page 88) gndt r5 ao/ai table 30 (page 88) gndt r15 o, ts, sl, id table 24 (page 82) gndt r17 i, id table 24 (page 82) gndt t17 ? table 34 (page 95) gndt u2 ? table 34 (page 95) gndt u4 ? table 34 (page 95) gndt u6 ? table 34 (page 95) gndt u10 ? table 34 (page 95) gndt u12 ? table 34 (page 95) gndt u14 ? table 34 (page 95) gndt u16 ? table 34 (page 95) gndt u17 ? table 34 (page 95) led0_1 k3 ? ? led0_2 k2 ? ? led0_3 j1 ? table 35 (page 97) led1_1 j4 ? table 35 (page 97) led1_2 j3 ? table 35 (page 97) led1_3 h1 i, id table 24 (page 82) led2_1 h2 o, ts, sl, id table 24 (page 82) led2_2 h3 i, id table 24 (page 82) led2_3 g1 o, ts, sl, id table 32 (page 90) led3_1 f2 od, ts, sl, ip table 33 (page 94) led3_2 g3 i, st, id table 32 (page 90) led3_3 g4 ? table 24 (page 82) led4_1 k16 ? ? led4_2 k17 ? ? signal ball type 1 reference for full description led4_3 j17 ? ? led5_1 j15 ? ? led5_2 j16 ? ? led5_3 h17 ? table 35 (page 97) led6_1 h15 ? table 35 (page 97) led6_2 h16 ? table 35 (page 97) led6_3 g17 ? table 24 (page 82) led7_1 g15 i, id table 24 (page 82) led7_2 f17 i/o, ts, sl, ip table 28 (page 87) led7_3 f16 i/o, ts, sl, ip table 28 (page 87) linkhold a17 o, ts, sl table 24 (page 82) mdc0 e1 ? table 34 (page 95) mdc1 b10 ? table 34 (page 95) mddis l1 ? ? mdint0 f1 od, ts, sl, ip table 33 (page 94) mdint1 c9 ? table 34 (page 95) mdio0 f3 od, ts, sl, ip table 33 (page 94) mdio1 a10 o, ts, sl table 24 (page 82) mdix d2 i, st table 34 (page 95) modesel0 l16 ? ? modesel1 l17 ? ? n/c a3 i, st, id table 32 (page 90) n/c a4 i, st, id table 32 (page 90) n/c a7 i, st, id table 32 (page 90) n/c a13 o, ts, sl table 24 (page 82) n/c a14 o, ts, sl table 24 (page 82) n/c a16 o, ts, sl table 24 (page 82) n/c b2 ? table 34 (page 95) n/c b6 ? table 34 (page 95) n/c b11 ? table 34 (page 95) n/c b14 ? table 34 (page 95) n/c c2 ? table 34 (page 95) n/c c6 ? table 34 (page 95) n/c c8 ? table 34 (page 95) n/c c10 ? table 34 (page 95) n/c c14 ? table 34 (page 95) signal ball type 1 reference for full description
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 74 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 n/c c15 ? table 34 (page 95) n/c d4 ? table 34 (page 95) n/c d9 ? table 34 (page 95) n/c d11 ? table 34 (page 95) n/c d16 ? table 34 (page 95) n/c e16 od, ts, sl, ip table 33 (page 94) n/c f4 od, ts, sl, ip table 33 (page 94) n/c f15 od, ts, sl, ip table 28 (page 87) n/c g2 i, st, id table 32 (page 90) n/c g5 i, id table 24 (page 82) n/c g14 ? table 24 (page 82) n/c g16 ? table 24 (page 82) n/c h4 i, id table 24 (page 82) n/c h14 ? table 35 (page 97) n/c j2 ? table 35 (page 97) n/c j13 ? ? n/c k4 ? ? n/c k15 ? ? no ball f6 od, ts, sl, ip table 33 (page 94) no ball f7 od, ts, sl, ip table 33 (page 94) no ball f8 od, ts, sl, ip table 33 (page 94) no ball e8 od, ts, sl, ip table 33 (page 94) no ball e10 od, ts, sl, ip table 33 (page 94) no ball f9 od, ts, sl, ip table 33 (page 94) no ball f10 od, ts, sl, ip table 33 (page 94) no ball f11 i, st, id table 28 (page 87) no ball f12 i, st, id table 28 (page 87) no ball g6 i, id table 24 (page 82) no ball g7 o, ts, sl, id table 24 (page 82) no ball g8 ? table 24 (page 82) no ball g9 i, id table 24 (page 82) signal ball type 1 reference for full description no ball g10 o, ts, sl, id table 24 (page 82) no ball g11 i, id table 24 (page 82) no ball g12 o, ts, sl, id table 24 (page 82) no ball h5 ? table 24 (page 82) no ball h6 i, id table 24 (page 82) no ball h7 o, ts, sl, id table 24 (page 82) no ball h11 ? table 24 (page 82) no ball h12 i, id table 24 (page 82) no ball h13 ? table 35 (page 97) no ball j6 ? table 35 (page 97) no ball j7 ? ? no ball j11 no ball j12 ? ? no ball k5 ? ? no ball k6 ? ? no ball k7 ? ? no ball k11 ? ? no ball k12 ? ? no ball k13 ? ? no ball l6 ? ? no ball l7 ? ? no ball l8 ? ? no ball l9 ? ? no ball l10 ? ? no ball l11 ? ? no ball l11 ? ? no ball m6 i table 24 (page 82) no ball m7 i table 24 (page 82) no ball m8 i, st, ip table 32 (page 90) no ball m9 i, id table 24 (page 82) no ball m10 o, ts table 24 (page 82) no ball m11 o, ts table 24 (page 82) no ball m12 o, ts table 24 (page 82) no ball n8 i table 29 (page 88) no ball n10 i, st, id table 32 (page 90) pause d5 i, st table 34 (page 95) signal ball type 1 reference for full description
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 75 document number: 249241 revision number: 007 revision date: august 28, 2003 preasel d7 i, st table 34 (page 95) pwrdwn l14 ? ? refclk0 e6 od, ts, sl, ip table 33 (page 94) refclk1 e12 od, ts, sl, ip table 33 (page 94) reset m15 o, ts, id table 24 (page 82) rxclk0 e3 ? table 34 (page 95) rxdata0 b1 i, st, id table 32 (page 90) rxdata1 b4 ? table 34 (page 95) rxdata2 c7 ? table 34 (page 95) rxdata3 b9 ? table 34 (page 95) rxdata4 c12 ? table 34 (page 95) rxdata5 b15 ? table 34 (page 95) rxdata6 b17 ? table 34 (page 95) rxdata7 f14 od, ts, sl, ip table 28 (page 87) sd_2p5v p1 ao/ai table 30 (page 88) sd0 p2 ao/ai table 30 (page 88) sd1 n4 i table 29 (page 88) sd2 p3 ao/ai table 30 (page 88) sd3 n5 i table 29 (page 88) sd4 p15 ao/ai table 30 (page 88) sd5 p16 ao/ai table 30 (page 88) sd6 p17 ao/ai table 30 (page 88) sd7 n17 ao/ai table 30 (page 88) section l15 ? ? sgnd k14 ? ? tck m16 o, ts, id table 24 (page 82) tdi n14 o, ts table 31 (page 89) tdo n15 i, st, ip table 31 (page 89) tms n16 ao/ai table 30 (page 88) tpfin0 t1 i, id table 24 (page 82) tpfin1 t4 i, id table 24 (page 82) tpfin2 t5 i, id table 24 (page 82) tpfin3 r8 ao/ai table 30 (page 88) tpfin4 u9 ? table 34 (page 95) tpfin5 t12 ? table 34 (page 95) tpfin6 t13 ? table 34 (page 95) signal ball type 1 reference for full description tpfin7 t16 ? table 34 (page 95) tpfip0 r2 ao/ai table 30 (page 88) tpfip1 u3 ? table 34 (page 95) tpfip2 r6 ao/ai table 30 (page 88) tpfip3 t8 i, st, id table 32 (page 90) tpfip4 t9 i, id table 24 (page 82) tpfip5 u13 ? table 34 (page 95) tpfip6 r12 ao/ai table 30 (page 88) tpfip7 r16 i, id table 24 (page 82) tpfon0 u1 ? table 34 (page 95) tpfon1 r4 ao/ai table 30 (page 88) tpfon2 u5 ? table 34 (page 95) tpfon3 t7 i, st, id table 32 (page 90) tpfon4 r10 ao/ai table 30 (page 88) tpfon5 u11 ? table 34 (page 95) tpfon6 u15 ? table 34 (page 95) tpfon7 t15 ? table 34 (page 95) tpfop0 t2 i, id table 24 (page 82) tpfop1 t3 i, id table 24 (page 82) tpfop2 t6 i, id table 24 (page 82) tpfop3 u7 ? table 34 (page 95) tpfop4 t10 i, id table 24 (page 82) tpfop5 t11 ? table 34 (page 95) tpfop6 t14 ? table 34 (page 95) tpfop7 r14 i, st, ip table 31 (page 89) trst m17 o, ts, id table 24 (page 82) txclk1 d17 ? table 34 (page 95) txdata0 e2 ? table 34 (page 95) txdata1 c3 ? table 34 (page 95) txdata2 b5 ? table 34 (page 95) txdata3 d8 ? table 34 (page 95) txdata4 a11 o, ts, sl table 24 (page 82) txdata5 b13 ? table 34 (page 95) txdata6 d13 ? table 34 (page 95) txdata7 e14 od, ts, sl, ip table 33 (page 94) txslew_0 n3 i table 29 (page 88) txslew_1 m4 o, ts, sl, id table 32 (page 90) signal ball type 1 reference for full description
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 76 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 txsync0 a6 i, st, ip table 32 (page 90) txsync1 c16 ? table 34 (page 95) vccd f5 od, ts, sl, ip table 33 (page 94) vccd g13 i, id table 24 (page 82) vccd j5 ? table 35 (page 97) vccd j14 ? ? vccio a2 i, st, id table 32 (page 90) vccio a8 i, st, id table 32 (page 90) vccio c1 ? table 34 (page 95) vccio c11 ? table 34 (page 95) vccio d14 ? table 34 (page 95) vccpecl l5 ? ? vccpecl l13 ? ? vccr n13 i, st, ip table 31 (page 89) vccr p4 ao/ai table 30 (page 88) vccr p7 ao/ai table 30 (page 88) vccr p8 ao/ai table 30 (page 88) vccr p9 ao/ai table 30 (page 88) vccr p10 ao/ai table 30 (page 88) vccr p11 ao/ai table 30 (page 88) vccr p12 ao/ai table 30 (page 88) vcct n6 i table 29 (page 88) vcct n7 i table 29 (page 88) vcct n9 i table 29 (page 88) vcct n11 ? table 34 (page 95) vcct n12 i, st, id table 31 (page 89) signal ball type 1 reference for full description
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 77 document number: 249241 revision number: 007 revision date: august 28, 2003 table 23. intel? lxt9785/lxt9785e ss-smii bga23 ball list in alphanumeric order by ball location ball symbol type 1 reference for full description a1 gndd ? table 34 (page 95) a2 vccio ? table 34 (page 95) a3 n/c o, ts table 24 (page 82) a4 n/c i, id table 24 (page 82) a5 crs_dv2 o, ts, sl table 24 (page 82) a6 txsync0 i, id table 24 (page 82) a7 n/c i, id table 24 (page 82) a8 vccio ? table 34 (page 95) a9 gndd ? table 34 (page 95) a10 mdio1 i/o, ts, sl, ip table 28 (page 87) a11 txdata4 i, id table 24 (page 82) a12 fifosel0 o, ts, sl, id, i, st table 24 (page 82) a13 n/c o, ts table 24 (page 82) a14 n/c i, id table 24 (page 82) a15 fifosel1 o, ts, sl, id, i, st table 24 (page 82) a16 n/c i, id table 24 (page 82) a17 linkhold o, ts, sl, id, i, st table 24 (page 82) b1 rxdata0 o, ts table 24 (page 82) b2 n/c i, id table 24 (page 82) b3 gndd ? table 34 (page 95) b4 rxdata1 o, ts, id table 24 (page 82) b5 txdata2 i, id table 24 (page 82) b6 n/c o, ts table 24 (page 82) b7 gndd ? table 34 (page 95) b8 crs_dv3 o, ts, sl table 24 (page 82) b9 rxdata3 o, ts, id table 24 (page 82) b10 mdc1 i, st, id table 28 (page 87) b11 n/c i, id table 24 (page 82) b12 crs_dv4 o, ts, sl table 24 (page 82) b13 txdata5 i, id table 24 (page 82) b14 n/c o, ts table 24 (page 82) b15 rxdata5 o, ts, id table 24 (page 82) b16 crs_dv6 o, ts, sl table 24 (page 82) b17 rxdata6 o, ts, id table 24 (page 82) c1 vccio ? table 34 (page 95) c2 n/c ? table 24 (page 82) c3 txdata1 i, id table 24 (page 82) c4 crs_dv1 o, ts, sl table 24 (page 82) c5 gndd ? table 34 (page 95) c6 n/c i, id table 24 (page 82) c7 rxdata2 o, ts, id table 24 (page 82) c8 n/c o, ts, sl, id table 24 (page 82) c9 mdint1 od, ts, sl, ip table 28 (page 87) c10 n/c i, id table 24 (page 82) c11 vccio ? table 34 (page 95) c12 rxdata4 o, ts,id table 24 (page 82) c13 gndd ? table 34 (page 95) c14 n/c i, id table 24 (page 82) c15 n/c o, ts table 24 (page 82) c16 txsync1 i, id table 24 (page 82) c17 gndd ? table 34 (page 95) d1 gndd ? table 34 (page 95) d2 mdix o, ts, sl, id, i, st table 32 (page 90) d3 gndd ? table 34 (page 95) d4 n/c i, id table 24 (page 82) d5 pause o, ts, sl, id, i, st table 32 (page 90) d6 gndd ? table 34 (page 95) d7 preasel o, ts, sl, id, i, st table 24 (page 82) d8 txdata3 i, id table 24 (page 82) d9 n/c o, ts table 24 (page 82) d10 gndd ? table 34 (page 95) d11 n/c i, id table 24 (page 82) d12 crs_dv5 o, ts, sl table 24 (page 82) d13 txdata6 i, id table 24 (page 82) d14 vccio ? table 34 (page 95) d15 gndd ? table 34 (page 95) ball symbol type 1 reference for full description
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 78 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 d16 n/c i, id table 24 (page 82) d17 txclk1 o, ts, sl, id table 24 (page 82) e1 mdc0 i, st, id table 28 (page 87) e2 txdata0 i, id table 24 (page 82) e3 rxclk0 i, id table 24 (page 82) e4 crs_dv0 o, ts, sl table 24 (page 82) e5 gndd ? table 34 (page 95) e6 refclk0 i table 24 (page 82) e7 gndd ? table 34 (page 95) e8 no ball ? ? e9 gndd ? table 34 (page 95) e10 no ball e11 gndd ? table 34 (page 95) e12 refclk1 i table 24 (page 82) e13 gndd ? table 34 (page 95) e14 txdata7 i, id table 24 (page 82) e15 crs_dv7 o, ts, sl table 24 (page 82) e16 n/c o, ts table 24 (page 82) e17 gndd ? table 34 (page 95) f1 mdint0 od, ts, sl, ip table 28 (page 87) f2 led3_1 od, ts, sl, ip table 33 (page 94) f3 mdio0 i/o, ts, sl, ip table 28 (page 87) f4 n/c i, id table 24 (page 82) f5 vccd ? table 34 (page 95) f6 no ball ? ? f7 no ball ? ? f8 no ball ? ? f9 no ball ? ? f10 no ball ? ? f11 no ball ? ? f12 no ball ? ? f13 gndd ? table 34 (page 95) f14 rxdata7 o, ts, id table 24 (page 82) f15 n/c ? table 35 (page 97) f16 led7_3 od, ts, sl, ip table 33 (page 94) ball symbol type 1 reference for full description f17 led7_2 od, ts, sl, ip table 33 (page 94) g1 led2_3 od, ts, sl, ip table 33 (page 94) g2 n/c ? table 35 (page 97) g3 led3_2 od, ts, sl, ip table 33 (page 94) g4 led3_3 od, ts, so, ip table 33 (page 94) g5 n/c ? table 35 (page 97) g6 no ball ? ? g7 no ball ? ? g8 no ball ? ? g9 no ball ? ? g10 no ball ? ? g11 no ball ? ? g12 no ball ? ? g13 vccd ? table 34 (page 95) g14 n/c ? table 35 (page 97) g15 led7_1 od, ts, sl, ip table 33 (page 94) g16 n/c ? table 35 (page 97) g17 led6_3 od, ts, sl, ip table 33 (page 94) h1 led1_3 od, ts, sl, ip table 33 (page 94) h2 led2_1 od, ts, sl, ip table 33 (page 94) h3 led2_2 od, ts, sl, ip table 33 (page 94) h4 n/c ? table 35 (page 97) h5 no ball ? ? h6 no ball ? ? h7 no ball ? ? h8 gndd ? table 34 (page 95) h9 gndd ? table 34 (page 95) h10 gndd ? table 34 (page 95) h11 no ball ? ? h12 no ball ? ? h13 no ball ? ? h14 n/c ? table 35 (page 97) ball symbol type 1 reference for full description
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 79 document number: 249241 revision number: 007 revision date: august 28, 2003 h15 led6_1 od, ts, sl, ip table 33 (page 94) h16 led6_2 od, ts, sl, ip table 33 (page 94) h17 led5_3 od, ts, sl, ip table 33 (page 94) j1 led0_3 od, ts, sl, ip table 33 (page 94) j2 n/c ? table 35 (page 97) j3 led1_2 od, ts, sl, ip table 33 (page 94) j4 led1_1 od, ts, sl, ip table 33 (page 94) j5 vccd ? table 34 (page 95) j6 no ball ? ? j7 no ball ? ? j8 gndd ? table 34 (page 95) j9 gndd ? table 34 (page 95) j10 gndd ? table 34 (page 95) j11 no ball ? ? j12 no ball ? ? j13 n/c ? table 35 (page 97) j14 vccd ? table 34 (page 95) j15 led5_1 od, ts, sl, ip table 33 (page 94) j16 led5_2 od, ts, sl, ip table 33 (page 94) j17 led4_3 od, ts, sl, ip table 33 (page 94) k1 amdix_en i, st, ip table 32 (page 90) k2 led0_2 od, ts, sl, ip table 33 (page 94) k3 led0_1 od, ts, sl, ip table 33 (page 94) k4 n/c ? table 35 (page 97) k5 no ball ? ? k6 no ball ? ? k7 no ball ? ? k8 gndd ? table 34 (page 95) k9 gndd ? table 34 (page 95) k10 gndd ? table 34 (page 95) k11 no ball ? ? ball symbol type 1 reference for full description k12 no ball ? ? k13 no ball ? ? k14 sgnd ? table 34 (page 95) k15 n/c ? table 35 (page 97) k16 led4_1 od, ts, sl, ip table 33 (page 94) k17 led4_2 od, ts, sl, ip table 33 (page 94) l1 mddis i, st, id table 28 (page 87) l2 cfg_3 i, st, id table 32 (page 90) l3 cfg_2 i, st, id table 32 (page 90) l4 add_4 i, st, id table 32 (page 90) l5 vccpecl ? table 34 (page 95) l6 no ball ? ? l7 no ball ? ? l8 no ball ? ? l9 no ball ? ? l10 no ball ? ? l11 no ball ? ? l11 no ball ? ? l13 vccpecl ? table 34 (page 95) l14 pwrdwn i, st, id table 32 (page 90) l15 section i, st, id table 32 (page 90) l16 modesel0 i, st, id table 32 (page 90) l17 modesel1 i, st, id table 32 (page 90) m1 cfg_1 i, st, id table 32 (page 90) m2 add_3 i, st, id table 32 (page 90) m3 add_2 i, st, id table 32 (page 90) m4 txslew_1 i, st, id table 32 (page 90) m5 gndpecl ? table 34 (page 95) m6 no ball ? ? m7 no ball ? ? m8 no ball ? ? m9 no ball ? ? m10 no ball ? ? m11 no ball ? ? m12 no ball ? ? m13 gndpecl ? table 34 (page 95) m14 g_fx/tp i, st, id table 32 (page 90) ball symbol type 1 reference for full description
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 80 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 m15 reset i, st, ip table 32 (page 90) m16 tck i, st, id table 31 (page 89) m17 trst i, st, ip table 31 (page 89) n1 add_1 i, st, id table 32 (page 90) n2 add_0 i, st, id table 32 (page 90) n3 txslew_0 i, st, id table 32 (page 90) n4 sd1 i table 29 (page 88) n5 sd3 i table 29 (page 88) n6 vcct ? table 34 (page 95) n7 vcct ? table 34 (page 95) n8 no ball ? ? n9 vcct ? table 34 (page 95) n10 no ball ? ? n11 vcct ? table 34 (page 95) n12 vcct ? table 34 (page 95) n13 vccr ? table 34 (page 95) n14 tdi i, st, ip table 31 (page 89) n15 tdo o, ts table 31 (page 89) n16 tms i, st, ip table 31 (page 89) n17 sd7 i table 29 (page 88) p1 sd_2p5v i, st, id table 29 (page 88) p2 sd0 i table 29 (page 88) p3 sd2 i table 29 (page 88) p4 vccr ? table 34 (page 95) p5 gndr ? table 34 (page 95) p6 gndr ? table 34 (page 95) p7 vccr ? table 34 (page 95) p8 vccr ? table 34 (page 95) p9 vccr ? table 34 (page 95) p10 vccr ? table 34 (page 95) p11 vccr ? table 34 (page 95) p12 vccr ? table 34 (page 95) p13 gndr ? table 34 (page 95) p14 gndt ? table 34 (page 95) p15 sd4 i table 29 (page 88) p16 sd5 i table 29 (page 88) p17 sd6 i table 29 (page 88) r1 gndt ? table 34 (page 95) ball symbol type 1 reference for full description r2 tpfip0 ao/ai table 30 (page 88) r3 gndt ? table 34 (page 95) r4 tpfon1 ao/ai table 30 (page 88) r5 gndt ? table 34 (page 95) r6 tpfip2 ao/ai table 30 (page 88) r7 gndr ? table 34 (page 95) r8 tpfin3 ao/ai table 30 (page 88) r9 gndr ? table 34 (page 95) r10 tpfon4 ao/ai table 30 (page 88) r11 gndr ? table 34 (page 95) r12 tpfip6 ao/ai table 30 (page 88) r13 gndr ? table 34 (page 95) r14 tpfop7 ao/ai table 30 (page 88) r15 gndt ? table 34 (page 95) r16 tpfip7 ao/ai table 30 (page 88) r17 gndt ? table 34 (page 95) t1 tpfin0 ao/ai table 30 (page 88) t2 tpfop0 ao/ai table 30 (page 88) t3 tpfop1 ao/ai table 30 (page 88) t4 tpfin1 ao/ai table 30 (page 88) t5 tpfin2 ao/ai table 30 (page 88) t6 tpfop2 ao/ai table 30 (page 88) t7 tpfon3 ao/ai table 30 (page 88) t8 tpfip3 ao/ai table 30 (page 88) t9 tpfip4 ao/ai table 30 (page 88) t10 tpfop4 ao/ai table 30 (page 88) t11 tpfop5 ao/ai table 30 (page 88) t12 tpfin5 ao/ai table 30 (page 88) t13 tpfin6 ao/ai table 30 (page 88) t14 tpfop6 ao/ai table 30 (page 88) t15 tpfon7 ao/ai table 30 (page 88) t16 tpfin7 ao/ai table 30 (page 88) t17 gndt ? table 34 (page 95) u1 tpfon0 ao/ai table 30 (page 88) u2 gndt ? table 34 (page 95) u3 tpfip1 ao/ai table 30 (page 88) u4 gndt ? table 34 (page 95) u5 tpfon2 ao/ai table 30 (page 88) ball symbol type 1 reference for full description
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 81 document number: 249241 revision number: 007 revision date: august 28, 2003 u6 gndt ? table 34 (page 95) u7 tpfop3 ao/ai table 30 (page 88) u8 gndr ? table 34 (page 95) u9 tpfin4 ao/ai table 30 (page 88) u10 gndt ? table 34 (page 95) u11 tpfon5 ao/ai table 30 (page 88) u12 gndt ? table 34 (page 95) u13 tpfip5 ao/ai table 30 (page 88) u14 gndt ? table 34 (page 95) u15 tpfon6 ao/ai table 30 (page 88) u16 gndt ? table 34 (page 95) u17 gndt ? table 34 (page 95) ball symbol type 1 reference for full description
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 82 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 3.4 bga23 signal descriptions 3.4.1 signal name conventions signal names may contain either a port designation or a serial designation, or a combination of the two designations. signal naming conventions are as follows: ? port number only. individual signals that apply to a particular port are designated by the signal mnemonic, immediately fo llowed by the port designa tion. for example, transmit enable signals would be identified as txen0, txen1, and txen2. ? serial number only. a set of signals which are not tied to any specific port are designated by the signal mnemonic, fo llowed by an underscore and a serial designation. for example, a set of three global configuration signals would be identified as cfg_1, cfg_2, and cfg_3. ? port and serial number. in cases where each port is assigned a set of multiple signals, each signal is designated in the following order: signal mnemonic, port designation, an underscore, and the serial designation. for exam ple, a set of three port configuration signals would be identified as rxdata0_0 and rxdata0_1, rxdata1_0 and rxdata1_1, and rxdata2_0 and rxdata2_1. 3.4.2 signal descriptions ? rmii, smii, and ss-smi i configurations table 24. intel ? lxt9785/lxt9785e rmii signal descriptions ? bga23 (sheet 1 of 3) ball/pin designation symbol type 1 signal description 2,3 bga23 pqfp e6, e12 44 6 refclk0 refclk1 i reference clock. 50 mhz rmii reference clock is always required. rmii inputs are sampled on the rising edge of refclk, rmii outputs are sourced on the falling edge. see ?clock/sync requirements? on page 125. for detailed clk requirements. e2, f4 61 62 txdata0_0 txdata0_1 i, id transmit data - port 0. inputs containing 2-bit parall el di-bits to be transmitted from port 0 are clocked in synchronously to refclk. c3, d4 52 53 txdata1_0 txdata1_1 i, id transmit data - port 1. inputs containing 2-bit parall el di-bits to be transmitted from port 1 are clocked in synchronously to refclk b5 a4 42 43 txdata2_0 txdata2_1 i, id transmit data - port 2. inputs containing 2-bit parall el di-bits to be transmitted from port 2 are clocked in synchronously to refclk. 1. type column coding: i = input, o = output, od = open drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull- down. 2. the ip/id resistors are disabled during h/w power-down mode. if a pin is an output or an i/o, the ip/id resistors are also disabled when the output is enabled. 3. rxdata[0:7]_0, rxdata[0:7]_1, crs_dv[0:7] and rxer[0:7] outputs are three-stated in isolation and h/w power-down modes and during h/w reset.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 83 document number: 249241 revision number: 007 revision date: august 28, 2003 d8, a6 34 35 txdata3_0 txdata3_1 i, id transmit data - port 3. inputs containing 2-bit parallel di-bits to be transmitted from port 3 are clocked in synchronously to refclk. a11, c10 22 23 txdata4_0 txdata4_1 i, id transmit data - port 4. inputs containing 2-bit parallel di-bits to be transmitted from port 4 are clocked in synchronously to refclk. b13, d11 13 14 txdata5_0 txdata5_1 i, id transmit data - port 5. inputs containing 2-bit parallel di-bits to be transmitted from port 5 are clocked in synchronously to refclk. d13, a16 4 5 txdata6_0 txdata6_1 i, id transmit data - port 6. inputs containing 2-bit parallel di-bits to be transmitted from port 6 are clocked in synchronously to refclk. e14, c16 203 204 txdata7_0 txdata7_1 i, id transmit data - port 7. inputs containing 2-bit parallel di-bits to be transmitted from port 7 are clocked in synchronously to refclk. e3, b2, c6, a7, b11, a14, c14, d16 60 51 41 33 21 12 3 202 txen0 txen1 txen2 txen3 txen4 txen5 txen6 txen7 i, id transmit enable - ports 0-7. active high input enables re spective port transmitter. this signal must be synchronous to the refclk. c2, b1 55 54 rxdata0_0 rxdata0_1 o, ts o, ts, id receive data - port 0. receive data signals (2-bit parallel di-bits) are driven synchronously to refclk. a3, b4 46 45 rxdata1_0 rxdata1_1 o, ts o, ts, id receive data - port 1. receive data signals (2-bit parallel di-bits) are driven synchronously to refclk. b6, c7 37 36 rxdata2_0 rxdata2_1 o, ts o, ts, id receive data - port 2. receive data signals (2-bit parallel di-bits) are driven synchronously to refclk. d9, b9 28 27 rxdata3_0 rxdata3_1 o, ts o, ts, id receive data - port 3. receive data signals (2-bit parallel di-bits) are driven synchronously to refclk. a13, c12 16 15 rxdata4_0 rxdata4_1 o, ts o, ts, id receive data - port 4. receive data signals (2-bit parallel di-bits) are driven synchronously to refclk. b14, b15 8 7 rxdata5_0 rxdata5_1 o, ts o, ts, id receive data - port 5. receive data signals (2-bit parallel di-bits) are driven synchronously to refclk. table 24. intel ? lxt9785/lxt9785e rmii signal descriptions ? bga23 (sheet 2 of 3) ball/pin designation symbol type 1 signal description 2,3 bga23 pqfp 1. type column coding: i = input, o = output, od = open drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull- down. 2. the ip/id resistors are disabled during h/w power-down mode. if a pin is an output or an i/o, the ip/id resistors are also disabled when the output is enabled. 3. rxdata[0:7]_0, rxdata[0:7]_1, crs_dv[0:7] and rxer[0:7] outputs are three-stated in isolation and h/w power-down modes and during h/w reset.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 84 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 c15, b17 206 205 rxdata6_0 rxdata6_1 o, ts o, ts, id receive data - port 6. receive data signals (2-bit pa rallel di-bits) are driven synchronously to refclk. e16, f14 198 197 rxdata7_0 rxdata7_1 o, ts o, ts, id receive data - port 7. receive data signals (2-bit pa rallel di-bits) are driven synchronously to refclk. e4, c4, a5, b8, b12, d12, b16, e15 58 49 39 31 17 10 1 200 crs_dv0 crs_dv1 crs_dv2 crs_dv3 crs_dv4 crs_dv5 crs_dv6 crs_dv7 o, ts, sl, id carrier sense/receive data valid - ports 0-7. on detection of valid carrier, these signals are asserted asynchronously with respect to refclk. crs_dvn is de-asserted on loss of carrier, synchronous to refclk. d2, d5, d7, c8, a12, a15, a17, d17 59 50 40 32 20 11 2 201 rxer0 rxer1 rxer2 rxer3 rxer4 rxer5 rxer6 rxer7 o, ts, sl, id, i, st receive error - ports 0-7. these signals are synchro nous to the respective refclk. active high indicates that received code group is invalid, or that pll is not locked. the rxer signals have the following additional function pins: rxer0 (mdix) rxer1 (pause) rxer2 (preasel) rxer4 (fifosel0) rxer5 (fifosel1) rxer6 {linkhold) table 24. intel ? lxt9785/lxt9785e rmii signal descriptions ? bga23 (sheet 3 of 3) ball/pin designation symbol type 1 signal description 2,3 bga23 pqfp 1. type column coding: i = input, o = output, od = open drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull- down. 2. the ip/id resistors are disabled during h/w power-down mode. if a pin is an output or an i/o, the ip/id resistors are also disabled when the output is enabled. 3. rxdata[0:7]_0, rxdata[0:7]_1, crs_dv[0:7] and rxer[0:7] outputs are three-stated in isolation and h/w power-down modes and during h/w reset.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 85 document number: 249241 revision number: 007 revision date: august 28, 2003 table 25. intel ? lxt9785/lxt9785e smii / ss-smii common signal descriptions ? bga23 ball/pin designation symbol type 1 signal description 2 bga23 pqfp e2, c3, b5, d8, a11, b13, d13, e14 61 52 42 34 22 13 4 203 txdata0 txdata1 txdata2 txdata3 txdata4 txdata5 txdata6 txdata7 i, id transmit data - ports 0-7. these serial input streams provide data to be transmitted to the network. the lxt9785/9785e clocks the data in synchronously to refclk. e6, e12 44 6 refclk0 refclk1 i reference clock. the lxt9785/9785e always requires a 125 mhz reference clock input. refer to functional description for detailed clock requirements. refclk0 and refclk1 are always connected regardless of sectionalization mode. 1. type column coding: i = input, o = output, od = open drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull- down. 2. the ip/id resistors are disabled during h/w power-down mode. table 26. intel ? lxt9785/lxt9785e smii specific signal descriptions ? bga23 pin/ball designation symbol type 1 signal description 2,3 bga23 pqfp a6, c16 35 204 sync0 sync1 i, id smii synchronization. the mac must generate a sync pulse every 10 refclk cycles to synchronize the smii. sync0 is used when 1x8 port sectionalization is selected. sync0 and sync1 are to be used when 2x4 port se ctionalization is chosen. c2, a3, b6, d9, a13, b14, c15, e16 55 46 37 28 16 8 206 198 rxdata0 rxdata1 rxdata2 rxdata3 rxdata4 rxdata5 rxdata6 rxdata7 o, ts receive data - ports 0-7 . these serial output streams provide data received from the network. the lxt9785/9785e drives the data out synchronously to rxclk. 1. type column coding: i = input, o = output, od = open drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull- down. 2. the ip/id resistors are disabled during h/w power-down mode. 3. rxdata[0:7] outputs are three-stated in isolation and hardware power-down modes and during hardware reset.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 86 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 table 27. intel ? lxt9785/lxt9785e ss-smii specific signal descriptions ? bga23 ball/pin designation symbol type 1 signal description 2,3 bga23 pqfp a6, c16 35 204 txsync0 txsync1 i, id ss-smii transmit synchronization. the mac must generate a txsync pulse every 10 txclk cycles to mark the start of txdata segments. txsync0 is used when 1x8 port sectionalization is selected. e4, b12 58 17 rxsync0 rxsync1 o, ts, id ss-smii receive synchronization. the lxt9785/9785e generates these pulses every 10 rxclk cycles to mark the start of rxdata segments for the mac. rxsync1 is used when 1x8 port secti onalization is selected. rxsync0 may not be used. these outputs are only enabled when ss-smii mode is enabled. c8, d17 32 201 txclk0 txclk1 i, id ss-smii transmit clock. the mac sources this 125 mhz clock as the timing reference for txdata and txsync. only txclk0 is used when 1x8 port sectionalization is selected. see ?clock/ sync requirements? on page 125. for detailed clock requirements. e3, b11 60 21 rxclk0 rxclk1 o, ts, id ss-smii receive clock. the lxt9785/9785e generates these clocks, based on refclk, to provide a timing reference for rxdata and rxsync to the mac. rxclk1 is used when 1x8 port sectionalization is selected. rxclk0 may not be used. see ?clock/sync requirements? on page 125. for detailed clock requirements . these outputs are only enabled when ss- smii mode is enabled. b1, b4, c7, b9, c12, b15, b17, f14 54 45 36 27 15 7 205 197 rxdata0 rxdata1 rxdata2 rxdata3 rxdata4 rxdata5 rxdata6 rxdata7 o, ts, id receive data - ports 0-7. these serial output streams provide data received from the network. the lxt9785/9785e drives the data out synchronously to refclk. 1. type column coding: i = input, o = output, od = open drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull- down. 2. the ip/id resistors are disabled during h/w power-down mode. if a pin is an output or an i/o, the ip/id resistors are also disabled when the output is enabled. 3. rxdata[0:7], rxsync[0:1], and rxclk[0:1] outputs are three-stated in isolation and h/w power-down modes and during h/w reset.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 87 document number: 249241 revision number: 007 revision date: august 28, 2003 table 28. intel ? lxt9785/lxt9785e mdio control interface signals ? bga23 ball/pin designation symbol type 1 signal description 2,3, 4 bga23 pqfp f3, a10 64 25 mdio0 mdio1 i/o, ts, sl, ip management data input/output. bidirectional serial data channel for communication between the phy and mac or switch asic. only mdio0 is used when 1x8 por t sectionalization is selected. in 2x4 port sectionalization mode, mdio0 accesses ports 0-3 and mdio1 accesses ports 4-7. refer to figure 21 ?intel? lxt9785/lxt9785e typical ss-smii quad sectionalization diagram? on page 140 . f1, c9 67 26 mdint0 mdint1 od, ts, sl, ip management data interrupt. when register bit 18.1 = 1, an active low output on this pin indicates status change. only mdint0 is used when 1x8 port sectionalization is selected. in 2x4 port sectionalization mode, mdint0 is associated with ports 0-3 and mdint1 is associated with ports 4-7. refer to figure 21 ?intel? lxt9785/lxt9785e typical ss-smii quad sectionalization diagram? on page 140 . e1, b10 63 24 mdc0 mdc1 i, st, id management data clock. clock for the mdio serial data channel. maximum frequency is 20 mhz. only m dc0 is used when 1x8 port sectionalization is selected. in 2x4 port sectionalization mode, mdc0 clocks ports 0-3 register accesses and mdc1 clocks po rts 4-7 register accesses. refer to figure 21 ?intel? lxt9785/lxt9785e typical ss-smii quad sectionalization diagram? on page 140 . l1 84 mddis i, st, id management disable. when mddis is tied high, the mdio port is completely disabled and the hardware control interface pins set their respective bits at power up and reset. when mddis is pulled low at power up or reset, via the internal pull-down resistor or by tieing it to ground, the hardware control interface pins control only the initial or ?default? values of their re spective register bits. after the power-up/reset cycle is complete, bit control reverts to the mdio serial channel. 1. type column coding: i = input, o = output, od = open drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull- down. 2. the ip/id resistors are disabled during h/w power-down mode. if a pin is an output or an i/o, the ip/id resistors are also disabled when the output is enabled. 3. mdio[0:1] and mdint [0:1] outputs are three-stated in h/w power-down mode and during h/w reset. 4. supports the 802.3 mdio register set. specific bits in the registers are referenced using an ?x.y? notation, where x is the register number (0-32) and y is the bit number (0-15).
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 88 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 table 29. intel ? lxt9785/lxt9785e signal detect ? bga23 ball/pin designation symbol type 1 signal description 2,3 bga23 pqfp p1 95 sd_2p5v i, st, id signal detect 2.5 volt interface. sd input threshold voltage select. tie to vccpecl = select 2.5 v lvpecl input levels float or tie to gndpecl = select 3.3 v lvpecl input levels p2, n4, p3, n5, p15, p16, p17, n17 96 97 100 101 161 162 165 166 sd0 sd1 sd2 sd3 sd4 sd5 sd6 sd7 i signal detect - ports 0-7. signal detect input from the fiber transceiver (these inputs are only active for ports operating in fiber mode). logic high = normal operation (the process of searching for receive idles for the purpose of bringing link up is initiated) logic low = link is declared lost 1. type column coding: i = input, o = output, od = open drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull- down. 2. the ip/id resistors are disabled during h/w power-down mode. 3. tie sd[0:7] inputs to gndpecl if unused. table 30. intel ? lxt9785/lxt9785e network interface signal descriptions ? bga23 ball/pin designation symbol type 1 signal description bga23 pqfp t2, u1, t3, r4, t6, u5, u7, t7, t10, r10, t11, u11, t14,u15, r14, t15 107, 108 111, 110 121, 122 125, 124 136, 137 140, 139 150, 151 154, 153 tpfop0, tpfon0 tpfop1, tpfon1 tpfop2, tpfon2 tpfop3, tpfon3 tpfop4, tpfon4 tpfop5, tpfon5 tpfop6, tpfon6 tpfop7, tpfon7 ao/ai twisted-pair/fiber outputs 2 , positive & negative, ports 0-7. during 100base-tx or 10base-t operation, tpfo pins drive 802.3 compliant pulses onto the line. during 100base-fx operation, tpfo pins produce differential lvpecl outputs for fiber transceivers. r2, t1, u3, t4, r6, t5, t8, r8, t9, u9, u13, t12, r12, t13, r16, t16 104, 105 115, 114 118, 119 129, 128 132, 133 143, 142 146, 147 157, 156 tpfip0, tpfin0 tpfip1, tpfin1 tpfip2, tpfin2 tpfip3, tpfin3 tpfip4, tpfin4 tpfip5, tpfin5 tpfip6, tpfin6 tpfip7, tpfin7 ai/ao twisted-pair/fiber inputs 3 , positive & negative, ports 0-7. during 100base-tx or 10base-t operation, tpfi pins receive differential 100base-tx or 10base-t signals from the line. during 100base-fx operation, tpfi pins receive differential lvpecl inputs from fiber transceivers. 1. type column coding: ai = analog input, ao = analog output. 2. switched to inputs (see tpfip/n description) when not in fiber mode and mdix is not active [that is, twisted-pair, non-crossover mdi mode]. 3. switched to outputs (see tpfop/n description) when not in fiber mode and mdix is not active [that is, twisted-pair, non-crossover mdi mode].
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 89 document number: 249241 revision number: 007 revision date: august 28, 2003 table 31. intel ? lxt9785/lxt9785e jtag test signal descriptions ? bga23 ball/pin designation symbol type 1 signal description 2,3 bga23 pqfp n14 167 tdi i, st, ip test data input. test data sampled with respect to the rising edge of tck. n15 168 tdo o, ts test data output. test data driven with respect to the falling edge of tck. n16 169 tms i, st, ip test mode select. m16 170 tck i, st, id test clock. clock input for jtag test. m17 171 trst i, st, ip test reset. reset input for jtag test. 1. type column coding: i = input, o = output, od = open drain, ts = three-state-able output, smt = schmitt triggered input, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull- down. 2. the ip/id resistors are disabled during h/w power-down mode. if a pin is an output or an i/o, the ip/id resistors are also disabled when the output is enabled. 3. tdo output is three-stated in h/w power-down mode and during h/w reset.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 90 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 table 32. intel ? lxt9785/lxt9785e miscellaneous signal descriptions ? bga23 (sheet 1 of 4) ball/pin designation symbol type 1 signal description 2 bga23 pqfp n3, m4 94 93 txslew_0 txslew_1 i, st, id tx output slew controls 0 and 1 defaults. these pins are read at startup or reset. their value at that time is used to set the default state of register bits 27.11:10 for all ports. these register bits can be read and overwritten after startup / reset. these pins select the tx output slew rate for all ports (rise and fall time) as follows: txslew_1 txslew_0 slew rate (rise and fall time) 0 0 3.3 ns 0 1 3.6 ns 1 0 3.9 ns 1 1 4.2 ns d5 50 pause id, i, st pause default. this pin is read at startup or reset. its value at that time is used to set the default state of register bit 4.10 for all ports. this register bi t can be read and overwritten after startup / reset. when high, the lxt9785/ 9785e advertises pause capabilities on all ports during auto-negotiation. this pin is shared with rmii- rxer1. an external pull- up resistor (see applications section for value) can be used to set pause active while rxer1 is three-stated during h/w reset. if no pull-up is used, the default pause state is set inactive via the internal pull-down resistor. l14 174 pwrdwn i, st, id power-down. when high, forces the lxt9785/9785e into global power-down mode. pin is not on jtag chain. m15 175 reset i, st, ip reset. this active low input is ored with the control register reset register bit 0.15. when held low, all outputs are forced to inactive state. pin is not on jtag chain. 1. type column coding: i = input, o = output, od = open drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull-down. 2. the ip/id resistors are disabled during hardware power-down mode.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 91 document number: 249241 revision number: 007 revision date: august 28, 2003 l4, m2, m3, n1, n2 88 89 90 91 92 add_4 add_3 add_2 add_1 add_0 i, st, id address <4:0>. sets base address. each port adds its port number (starting with 0) to this address to determine its phy address. port 0 address = base port 1 address = base + 1 port 2 address = base + 2 port 3 address = base + 3 port 4 address = base + 4 port 5 address = base + 5 port 6 address = base + 6 port 7 address = base + 7 l17, l16 178 177 modesel_1 modesel_0 i, st, id mode select[1:0]. 00 = rmii 01 = smii 10 = ss-smii 11 = reserved all ports are configured the same. interfaces cannot be mixed and must be all rmii, smii, or ss-smii. l15 176 section i, st, id sectionalization select. this pin selects sectionalization into separate ports. 0 = 1x8 ports, 1 = 2x4 ports k1 83 amdix_en i, st, ip auto mdi/mdix enable default. this pin is read at startup or reset. its value at that time is used to set the default state of register bit 27.9 for all ports. these register bits can be read and overwritten after startup / reset. refer to table 40 ?intel? lxt9785/lxt9785e mdix selection? on page 119 . when active (high), automatic mdi crossover (mdix) (regardless of segmentation) is selected for all ports. when inactive (low) mdix is selected according to the mdix pin. table 32. intel ? lxt9785/lxt9785e miscellaneous signal descriptions ? bga23 (sheet 2 of 4) ball/pin designation symbol type 1 signal description 2 bga23 pqfp 1. type column coding: i = input, o = output, od = open drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-u p, id = weak internal pull-down. 2. the ip/id resistors are disabled during hardware power-down mode.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 92 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 d2 59 mdix i, id, st mdix select default. this pin is read at startup or reset. its value at that time is used to set the default state of register bit 27.8 for all ports. these register bits can be read and overwritten after startup / reset. refer to table 40 ?intel? lxt9785/lxt9785e mdix selection? on page 119 . when amdix_en is active this pin is ignored. when amdix_en is inactive, all ports are forced to the mdi or the mdix function regardless of segmentation. if this pin is active (high) , mdi crossover (mdix) is selected. if this pin is inactive, non-crossover mdi mode is set. this pin is shared with rmii- rxer0. an external pull- up resistor (see applications section for value) can be used to set mdix active while rxer0 is three-stated during h/w reset. if no pull-up is used, the default mdix state is set inactive via the internal pull-down resistor. do not tie this pin directly to vccio (vs. using a pull-up) in non-rmii modes. l2, l3, m1 85 86 87 cfg_3 cfg_2 cfg_1 i, st, id global port configuration defaults 1-3. these pins are read at startup or reset. their value at that time is used to set the default state of register bits shown in table 42 ?intel? lxt9785/9785e global hardware configuration settings? on page 129 for all ports. these register bits can be read and overwritten after startup / reset. when operating in hardware control mode, these pins provide configuration contro l options for all the ports (refer to table 42 ?intel? lxt9785/9785e global hardware configuration settings? on page 129 for details). m14 173 g_fx/tp i, st, id global fx/tp enable default. this pin is read at startup or reset. its value at that time is used to set the default state of register bit 16.0 for all ports. these register bits can be read and overwritten after startup / reset. refer to table 92 ?port configuration register (address 16, hex 10)? on page 207 . this input selects whether all the ports are defaulted to tp vs. fx mode. table 32. intel ? lxt9785/lxt9785e miscellaneous signal descriptions ? bga23 (sheet 3 of 4) ball/pin designation symbol type 1 signal description 2 bga23 pqfp 1. type column coding: i = input, o = output, od = open drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull-down. 2. the ip/id resistors are disabled during hardware power-down mode.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 93 document number: 249241 revision number: 007 revision date: august 28, 2003 a15 a12 11 20 fifosel1 fifosel0 i, id, st fifo select <1:0>. these pins are read at startup or reset. their value at that time is used to set the default state of register bits 18.15:14 for all ports. these register bits can be read and overwritten after startup/reset. these pins are shared with rmii-rxer<5:4>. an external pull-up resistor (see applications section for value) can be used to set fifo select<1:0> to active while rxer<5:4> are three-stated during hardware reset. if no pull-up is used, the default fifo select state is set via the internal pull-down resistors. see table 36 ?intel? lxt9785/lxt9785e receive fifo depth configurations? on page 97 . d7 40 preasel i, id, st preamble select. this pin is read at startup or reset. its value at that time is used to set the default state of register bit 16.5 for all ports. this register bit can be read and overwritten after startup/reset. this pin is shared with rm ii-rxer2. an external pull- up resistor (see applications section for value) can be used to set preamble select to active while rxer2 is three-stated during hardware reset. if no pull-up is used, the default preamble select state is set via the internal pull-down resistors. note: preamble select has no effect in 100 mbps operation. a17 2 linkhold i, id, st linkhold defaul t. this pin is read at startup or reset. its value at that time is used to set the default state of register bit 0.11 for all ports. this register bit can be read and overwritten after startup / reset. when high, the lxt9785/9785e powers down all ports. this pin is shared with rm ii-rxer6. an external pull- up resistor (see applications section for value) can be used to set linkhold active while rxer6 is tri-stated during h/w reset. if no pull-up is used, the default linkhold state is set inac tive via the internal pull- down resistor. table 32. intel ? lxt9785/lxt9785e miscellaneous signal descriptions ? bga23 (sheet 4 of 4) ball/pin designation symbol type 1 signal description 2 bga23 pqfp 1. type column coding: i = input, o = output, od = open drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-u p, id = weak internal pull-down. 2. the ip/id resistors are disabled during hardware power-down mode.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 94 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 table 33. intel ? lxt9785/lxt9785e led signal descriptions ? bga23 (sheet 1 of 2) ball/pin designation symbol type 1 signal description 2,3 bga23 pqfp k3, k2, j1 82 81 80 led0_1 led0_2 led0_3 od, ts, sl, ip port 0 led drivers 1-3. these pins drive led indicators for port 0. each led can display one of several av ailable status conditions as selected by the led configuration register (refer to table 96 ?led configuration register (address 20, hex 14)? on page 213 for details). j4, j3, h1 77 76 75 led1_1 led1_2 led1_3 od, ts, sl, ip port 1 led drivers 1-3. these pins drive led indicators for port 1. each led can display one of several av ailable status conditions as selected by the led configuration register (refer to table 96 ?led configuration register (address 20, hex 14)? on page 213 for details). h2, h3, g1 73 72 71 led2_1 led2_2 led2_3 od, ts, sl, ip port 2 led drivers 1-3. these pins drive led indicators for port 2. each led can display one of several av ailable status conditions as selected by the led configuration register (refer to table 96 ?led configuration register (address 20, hex 14)? on page 213 for details). f2, g3, g4 70 69 68 led3_1 led3_2 led3_3 od, ts, sl, ip port 3 led drivers 1-3. these pins drive led indicators for port 3. each led can display one of several av ailable status conditions as selected by the led configuration register (refer to table 96 ?led configuration register (address 20, hex 14)? on page 213 for details). k16, k17, j17 180 181 182 led4_1 led4_2 led4_3 od, ts, sl, ip port 4 led drivers 1-3. these pins drive led indicators for port 4. each led can display one of several av ailable status conditions as selected by the led configuration register (refer to table 96 ?led configuration register (address 20, hex 14)? on page 213 for details). 1. type column coding: i = input, o = output, od = open drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull- down. 2. the ip/id resistors are disabled during h/w power-down mode. if a pin is an output or an i/o, the ip/id resistors are also disabled when the output is enabled. 3. the led outputs are three-stated in h/w power-down mode and during h/w reset. 4.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 95 document number: 249241 revision number: 007 revision date: august 28, 2003 j15, j16, h17 185 186 187 led5_1 led5_2 led5_3 od, ts, sl, ip port 5 led drivers 1-3. these pins drive led indicators for port 5. each led can display one of several available status conditions as selected by the led configuration register (refer to table 96 ?led configuration register (address 20, hex 14)? on page 213 for details). h15, h16, g17 189 190 191 led6_1 led6_2 led6_3 od, ts, sl, ip port 6 led drivers 1-3. these pins drive led indicators for port 6. each led can display one of several available status conditions as selected by the led configuration register (refer to table 96 ?led configuration register (address 20, hex 14)? on page 213 for details). g15, f17, f16 192 193 194 led7_1 led7_2 led7_3 od, ts, sl, ip port 7 led drivers 1-3. these pins drive led indicators for port 7. each led can display one of several available status conditions as selected by the led configuration register (refer to table 96 ?led configuration register (address 20, hex 14)? on page 213 for details). table 34. intel ? lxt9785/lxt9785e power supply signal descriptions ? bga23 (sheet 1 of 2) ball/pin designation symbol type signal description bga23 pqfp g13, j14, f5, j5 65, 78, 184, 196 vccd - digital power supply - core. +2.5 v supply for core digital circuits. a2, a8, c1, c11, d14 18, 29, 47, 56, 208 vccio - digital power supply - i/o ring. +2.5/3.3 v supply for digital i/o circuits. the digital input circuits running off of this rail, having a ttl-level threshold and over-voltage protection, may be interfaced with 3.3/5.0 v, when the io supply is 3.3 v, and 2.5/3.3/5.0 v when 2.5 v. l13, l5 98, 164 vccpecl - digital power supply - pecl signal detect inputs. +2.5/3.3 v supply for pecl signal detect input circuits. if fiber mode is not used, tie these pins to gndpecl to save power. n13, p4, p7, p8, p9, p10, p11, p12 103, 116, 117, 130, 131, 144, 145, 158 vccr - analog power supply - receive. +2.5 v supply for all analog receive circuits. 1. type column coding: i = input, o = output, od = open drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull- down. table 33. intel ? lxt9785/lxt9785e led signal descriptions ? bga23 (sheet 2 of 2) ball/pin designation symbol type 1 signal description 2,3 bga23 pqfp 1. type column coding: i = input, o = output, od = open drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull- down. 2. the ip/id resistors are disabled during h/w power-down mode. if a pin is an output or an i/o, the ip/id resistors are also disabled when the output is enabled. 3. the led outputs are three-stated in h/w power-down mode and during h/w reset. 4.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 96 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 n6, n7, n9, n11, n12 109, 123, 138, 152 vcct - analog power supply - transmit. +2.5 v supply for all analog transmit circuits. a1, a9, b3, b7, c5, c13, c17, d1, d3, d6, d10, d15, e5, e7, e9, e11, e13, e17, f13, h8, h9, h10, j8, j9, j10, k8, k9, k10 66, 79, 183, 195 gndd - digital ground. ground return for core digital supplies (vccd). all ground pins can be tied together using a single ground plane. 9, 19, 30, 38, 48, 57, 74, 188, 199, 207 gndio - digital gnd - i/o ring. ground return for digital i/o circuits (vccio). m5, m13 99, 163 gndpecl - digital gnd - pecl signal detect inputs. ground return for pecl signal detect input circuits. p5, p6, p13, r7, r9, r11, r13, u8 106, 112, 120, 126, 135, 141, 149, 155 gndr - analog ground - receive. ground return for receive analog supply. all ground pins can be tied together using a single ground plane. p14, r1, r3, r5, r15, r17, t17, u2, u4, u6, u10, u12, u14, u16, u17 113, 127, 134, 148 gndt - analog ground - transmit. ground return for transmit analog supply. all ground pins can be tied together using a single ground plane. k14 179 sgnd - substrate ground. ground for chip substrate. all ground pins can be tied together using a single ground plane. table 34. intel ? lxt9785/lxt9785e power supply signal descriptions ? bga23 (sheet 2 of 2) ball/pin designation symbol type signal description bga23 pqfp 1. type column coding: i = input, o = output, od = open drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull- down.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 97 document number: 249241 revision number: 007 revision date: august 28, 2003 table 35. intel ? lxt9785/lxt9785e unused/reserved pins ? bga23 pin/ball designation symbol type 1 signal description bga23 pqfp f15, g2, g5, g14, g16, h4, h14, j2, j13, k4, k15 n/c n/c ? no connection. 1. type column coding: i = input, o = output, od = open drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull- down 2. table 36. intel ? lxt9785/lxt9785e receive fifo depth configurations fifosel1 fifosel0 register 18.15 value register 18.14 value 00 10 01 11 10 00 11 01
98 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 intel ? lxt9785 and intel ? lxt9785e advanced 8-port 10/100 mbps phy transceivers 3.5 bga15 ball assignments the following figure and tables provide the bga15 ball locations and signal names arranged in alphanumeric order as follows: ? figure 6 ?intel? lxt9785mbc 196-ball bga15 assignments (top view)? ? table 37, ?intel? lxt9785mbc bga15 ball list in alphanumeric order by signal name? on page 99 ? table 38, ?intel? lxt9785mbc bga15 ball list in alphanumeric order by ball location (smii/ss-smii)? on page 103 figure 6. intel ? lxt9785mbc 196-ball bga15 assignments (top view) b1532-01 a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b c d e f g h j k l m n p a b c d e f g h j k l m n p p6 p5 p4 p3 p2 p1 n6 n5 n4 n3 n2 n1 m6 m5 m4 m3 m2 m1 l6 l5 l4 l3 l2 l1 k6 k5 k4 k3 k2 k1 j6 j5 j4 j3 j2 j1 h6 h5 h4 h3 h2 h1 g6 g5 g4 g3 g2 g1 f14 f13 f12 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 e14 e13 e12 e11 e10 e9 e8 e7 e6 e5 e4 e3 e2 e1 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 c14 c13 c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b1 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 b2 g7 g8 g9 g10 g11 g12 g13 g14 h7 h8 h9 h10 h11 h12 h13 h14 j7 k7 l7 m7 j8 k8 l8 m8 j9 k9 l9 m9 j10 k10 l10 m10 j11 k11 l11 m11 j12 k12 l12 m12 j13 k13 l13 m13 j14 k14 l14 m14 n7 p7 n8 p8 n9 p9 n10 p10 n11 p11 n12 p12 n13 p13 n14 p14
intel ? lxt9785 and intel ? lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 99 document number: 249241 revision number: 007 revision date: august 28, 2003 3.5.1 bga15 ball list the following tables provide the rmii bga23 ball locations and signal names arranged in alphanumeric order as follows: table 37 ?intel? lxt9785mbc bga15 ball list in alphanumeric order by signal name? table 38 ?intel? lxt9785mbc bga15 ball list in alphanumeric order by ball location (smii/ ss-smii)? table 37. intel? lxt9785mbc bga15 ball list in alphanumeric order by signal name signal name ball type reference for full description add_3 p10 i, st, id table 39 on page 109 add_4 n10 i, st, id table 39 on page 109 amdix_en k8 i, st, ip table 39 on page 109 avcc d12 ? table 39 on page 109 avcc e12 ? table 39 on page 109 avcc f12 ? table 39 on page 109 avcc g12 ? table 39 on page 109 avcc h12 ? table 39 on page 109 avcc j12 ? table 39 on page 109 avcc k12 ? table 39 on page 109 avcc l12 ? table 39 on page 109 avss e11 ? table 39 on page 109 avss f9 ? table 39 on page 109 avss f10 ? table 39 on page 109 avss f11 ? table 39 on page 109 avss g9 ? table 39 on page 109 avss g10 ? table 39 on page 109 avss g11 ? table 39 on page 109 avss h9 ? table 39 on page 109 avss h10 ? table 39 on page 109 avss h11 ? table 39 on page 109 avss j9 ? table 39 on page 109 avss j10 ? table 39 on page 109 avss j11 ? table 39 on page 109 avss k11 ? table 39 on page 109 avss l11 ? table 39 on page 109 cfg_1 m10 i, st, id table 39 on page 109 cfg_2 l9 i, st, id table 39 on page 109 cfg_3 m9 i, st, id table 39 on page 109 fifosel0 f1 i, id table 39 on page 109 fifosel1 c1 i, id table 39 on page 109 gndd a1 ? table 39 on page 109 gndd a2 ? table 39 on page 109 gndd a3 ? table 39 on page 109 gndd b1 ? table 39 on page 109 gndd b2 ? table 39 on page 109 gndd b5 ? table 39 on page 109 gndd b10 ? table 39 on page 109 gndd d9 ? table 39 on page 109 gndd d11 ? table 39 on page 109 gndd e5 ? table 39 on page 109 gndd e6 ? table 39 on page 109 gndd e9 ? table 39 on page 109 gndd e10 ? table 39 on page 109 gndd f5 ? table 39 on page 109 gndd f6 ? table 39 on page 109 gndd f7 ? table 39 on page 109 gndd f8 ? table 39 on page 109 gndd g4 ? table 39 on page 109 gndd g6 ? table 39 on page 109 gndd g7 ? table 39 on page 109 gndd g8 ? table 39 on page 109 gndd h6 ? table 39 on page 109 gndd h7 ? table 39 on page 109 gndd h8 ? table 39 on page 109 gndd j5 ? table 39 on page 109 signal name ball type reference for full description
100 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 intel ? lxt9785 and intel ? lxt9785e advanced 8-port 10/100 mbps phy transceivers gndd j6 ? table 39 on page 109 gndd j7 ? table 39 on page 109 gndd j8 ? table 39 on page 109 gndd k5 ? table 39 on page 109 gndd k6 ? table 39 on page 109 gndd k9 ? table 39 on page 109 gndd k10 ? table 39 on page 109 gndd l2 ? table 39 on page 109 gndd n1 ? table 39 on page 109 gndd n11 ? table 39 on page 109 gndd p1 ? table 39 on page 109 gndd p11 ? table 39 on page 109 led0_1 n9 od, ts, sl, ip table 39 on page 109 led0_2 p9 od, ts, sl, ip table 39 on page 109 led1_1 n8 od, ts, sl, ip table 39 on page 109 led1_2 p8 od, ts, sl, ip table 39 on page 109 led2_1 p7 od, ts, sl, ip table 39 on page 109 led2_2 n7 od, ts, sl, ip table 39 on page 109 led3_1 p6 od, ts, sl, ip table 39 on page 109 led3_2 n6 od, ts, sl, ip table 39 on page 109 led4_1 b9 od, ts, sl, ip table 39 on page 109 led4_2 a9 od, ts, sl, ip table 39 on page 109 led5_1 b8 od, ts, sl, ip table 39 on page 109 led5_2 a8 od, ts, sl, ip table 39 on page 109 signal name ball type reference for full description led6_1 a7 od, ts, sl, ip table 39 on page 109 led6_2 b7 od, ts, sl, ip table 39 on page 109 led7_1 b6 od, ts, sl, ip table 39 on page 109 led7_2 a6 od, ts, sl, ip table 39 on page 109 linkhold b3 id table 39 on page 109 mdc p4 i, st, id table 39 on page 109 mdint p5 od, ts, sl, ip table 39 on page 109 mdio n5 io, ts, sl, ip table 39 on page 109 modesel_0 c9 i, st, id table 39 on page 109 modesel_1 e8 i, st, id table 39 on page 109 n/c c4 ? table 39 on page 109 n/c c7 ? table 39 on page 109 n/c d1 ? table 39 on page 109 n/c d2 ? table 39 on page 109 n/c d5 ? table 39 on page 109 n/c d6 ? table 39 on page 109 n/c d8 ? table 39 on page 109 n/c d10 ? table 39 on page 109 n/c e4 ? table 39 on page 109 n/c e7 ? table 39 on page 109 n/c g2 ? table 39 on page 109 n/c g5 ? table 39 on page 109 n/c h1 ? table 39 on page 109 n/c h5 ? table 39 on page 109 n/c j4 ? table 39 on page 109 n/c k4 ? table 39 on page 109 n/c k7 ? table 39 on page 109 n/c l1 ? table 39 on page 109 n/c l6 ? table 39 on page 109 n/c l8 ? table 39 on page 109 signal name ball type reference for full description
intel ? lxt9785 and intel ? lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 101 document number: 249241 revision number: 007 revision date: august 28, 2003 n/c l10 ? table 39 on page 109 n/c m4 ? table 39 on page 109 n/c m5 ? table 39 on page 109 n/c m6 ? table 39 on page 109 n/c m7 ? table 39 on page 109 n/c m8 ? table 39 on page 109 n/c p2 ? table 39 on page 109 n/c p3 ? table 39 on page 109 refclk0 l4 i table 39 on page 109 refclk1 c3 i table 39 on page 109 reset c10 i, st, ip table 39 on page 109 rxclk g1 o, ts, id table 39 on page 109 rxdata0_s n3 o, ts table 39 on page 109 rxdata0_ss m3 o, ts, id table 39 on page 109 rxdata1_s m2 o, ts table 39 on page 109 rxdata1_ss m1 o, ts, id table 39 on page 109 rxdata2_s k2 o, ts table 39 on page 109 rxdata2_ss j2 o, ts, id table 39 on page 109 rxdata3_s h3 o, ts table 39 on page 109 rxdata3_ss h2 o, ts, id table 39 on page 109 rxdata4_s f2 o, ts table 39 on page 109 rxdata4_ss f3 o, ts, id table 39 on page 109 rxdata5_s e3 o, ts table 39 on page 109 rxdata5_ss c2 o, ts table 39 on page 109 rxdata6_s b4 o, ts table 39 on page 109 rxdata6_ss a4 o, ts, id table 39 on page 109 rxdata7_s c5 o, ts table 39 on page 109 rxdata7_ss c6 o, ts, id table 39 on page 109 rxsync e1 o, ts, id table 39 on page 109 sgnd c8 ? table 39 on page 109 sync/ txsync k1 i, id table 39 on page 109 signal name ball type reference for full description tck a11 i, st, id table 39 on page 109 tdi c12 i, st, ip table 39 on page 109 tdo c11 o, ts table 39 on page 109 tms b11 i, st, ip table 39 on page 109 tpin0 n12 ai/ao table 39 on page 109 tpin1 m13 ai/ao table 39 on page 109 tpin2 l14 ai/ao table 39 on page 109 tpin3 h13 ai/ao table 39 on page 109 tpin4 g13 ai/ao table 39 on page 109 tpin5 d14 ai/ao table 39 on page 109 tpin6 c13 ai/ao table 39 on page 109 tpin7 b12 ai/ao table 39 on page 109 tpip0 p12 ai/ao table 39 on page 109 tpip1 m14 ai/ao table 39 on page 109 tpip2 l13 ai/ao table 39 on page 109 tpip3 h14 ai/ao table 39 on page 109 tpip4 g14 ai/ao table 39 on page 109 tpip5 d13 ai/ao table 39 on page 109 tpip6 c14 ai/ao table 39 on page 109 tpip7 a12 ai/ao table 39 on page 109 tpon0 n13 ao/ai table 39 on page 109 tpon1 p14 ao/ai table 39 on page 109 tpon2 k14 ao/ai table 39 on page 109 tpon3 j13 ao/ai table 39 on page 109 tpon4 f13 ao/ai table 39 on page 109 tpon5 e14 ao/ai table 39 on page 109 tpon6 a14 ao/ai table 39 on page 109 tpon7 b13 ao/ai table 39 on page 109 tpop0 p13 ao/ai table 39 on page 109 tpop1 n14 ao/ai table 39 on page 109 tpop2 k13 ao/ai table 39 on page 109 tpop3 j14 ao/ai table 39 on page 109 tpop4 f14 ao, ai table 39 on page 109 tpop5 e13 ao/ai table 39 on page 109 tpop6 b14 ao/ai table 39 on page 109 tpop7 a13 ao/ai table 39 on page 109 signal name ball type reference for full description
102 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 intel ? lxt9785 and intel ? lxt9785e advanced 8-port 10/100 mbps phy transceivers trst a10 i, st, ip table 39 on page 109 txclk j3 i, id table 39 on page 109 txdata0 n4 i, id table 39 on page 109 txdata1 n2 i, id table 39 on page 109 txdata2 k3 i, id table 39 on page 109 txdata3 j1 i, id table 39 on page 109 txdata4 g3 i, id table 39 on page 109 txdata5 e2 i, id table 39 on page 109 txdata6 d3 i, id table 39 on page 109 txdata7 a5 i, id table 39 on page 109 txslew_0 m11 i, st, id table 39 on page 109 txslew_1 m12 i,st, id table 39 on page 109 vccd d7 ? table 39 on page 109 vccd l7 ? table 39 on page 109 vccio d4 ? table 39 on page 109 vccio f4 ? table 39 on page 109 vccio h4 ? table 39 on page 109 vccio l3 ? table 39 on page 109 vccio l5 ? table 39 on page 109 signal name ball type reference for full description
intel ? lxt9785 and intel ? lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 103 document number: 249241 revision number: 007 revision date: august 28, 2003 table 38 shows the ball locations and signal names arranged in order by ball location. table 38. intel? lxt9785mbc bga15 ball list in alphanumeric order by ball location (smii/ ss-smii) ball signal name type reference for full description a1 gndd ? table 39 on page 109 a2 gndd ? table 39 on page 109 a3 gndd ? table 39 on page 109 a4 rxdata6_ss o, ts, id table 39 on page 109 a5 txdata7 i, id table 39 on page 109 a6 led7_2 od, ts, sl, ip table 39 on page 109 a7 led6_1 od, ts, sl, ip table 39 on page 109 a8 led5_2 od, ts, sl, ip table 39 on page 109 a9 led4_2 od, ts, sl, ip table 39 on page 109 a10 trst i, st, ip table 39 on page 109 a11 tck i, st, id table 39 on page 109 a12 tpip7 ai/ao table 39 on page 109 a13 tpop7 ao/ai table 39 on page 109 a14 tpon6 ao/ai table 39 on page 109 b1 gndd ? table 39 on page 109 b2 gndd ? table 39 on page 109 b3 linkhold id table 39 on page 109 b4 rxdata6_s o, ts table 39 on page 109 b5 gndd ? table 39 on page 109 b6 led7_1 od, ts, sl, ip table 39 on page 109 b7 led6_2 od, ts, sl, ip table 39 on page 109 b8 led5_1 od, ts, sl, ip table 39 on page 109 b9 led4_1 od, ts, sl, ip table 39 on page 109 b10 gndd ? table 39 on page 109 b11 tms i, st, ip table 39 on page 109 b12 tpin7 ai/ao table 39 on page 109 b13 tpon7 ao/ai table 39 on page 109 b14 tpop6 ao/ai table 39 on page 109 c1 fifosel1 i, id table 39 on page 109 c2 rxdata5_ss o, ts, id table 39 on page 109 c3 refclk1 i table 39 on page 109 c4 n/c ? table 39 on page 109 c5 rxdata7_s o, ts table 39 on page 109 c6 rxdata7_ss o, ts, id table 39 on page 109 c7 n/c ? table 39 on page 109 c8 sgnd ? table 39 on page 109 c9 modesel_0 i, st, id table 39 on page 109 c10 reset i, st, ip table 39 on page 109 c11 tdo o, ts table 39 on page 109 c12 tdi i, st, ip table 39 on page 109 c13 tpin6 ai/ao table 39 on page 109 ball signal name type reference for full description
104 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 intel ? lxt9785 and intel ? lxt9785e advanced 8-port 10/100 mbps phy transceivers c14 tpip6 ai/ao table 39 on page 109 d1 n/c ? table 39 on page 109 d2 n/c ? table 39 on page 109 d3 txdata6 i, id table 39 on page 109 d4 vccio ? table 39 on page 109 d5 n/c ? table 39 on page 109 d6 n/c ? table 39 on page 109 d7 vccd ? table 39 on page 109 d8 n/c ? table 39 on page 109 d9 gndd ? table 39 on page 109 d10 n/c ? table 39 on page 109 d11 gndd ? table 39 on page 109 d12 avcc ? table 39 on page 109 d13 tpip5 ai/ao table 39 on page 109 d14 tpin5 ai/ao table 39 on page 109 e1 rxsync o, ts, id table 39 on page 109 e2 txdata5 i, id table 39 on page 109 e3 rxdata5_s o, ts table 39 on page 109 e4 n/c ? table 39 on page 109 e5 gndd ? table 39 on page 109 e6 gndd ? table 39 on page 109 e7 n/c ? table 39 on page 109 e8 modesel_1 i, st, id table 39 on page 109 e9 gndd ? table 39 on page 109 ball signal name type reference for full description e10 gndd ? table 39 on page 109 e11 avss ? table 39 on page 109 e12 avcc ? table 39 on page 109 e13 tpop5 ao/ai table 39 on page 109 e14 tpon5 ao/ai table 39 on page 109 f1 fifosel0 i, id table 39 on page 109 f2 rxdata4_s o, ts table 39 on page 109 f3 rxdata4_ss o, ts, id table 39 on page 109 f4 vccio ? table 39 on page 109 f5 gndd ? table 39 on page 109 f6 gndd ? table 39 on page 109 f7 gndd ? table 39 on page 109 f8 gndd ? table 39 on page 109 f9 avss ? table 39 on page 109 f10 avss ? table 39 on page 109 f11 avss ? table 39 on page 109 f12 avcc ? table 39 on page 109 f13 tpon4 ao/ai table 39 on page 109 f14 tpop4 ao, ai table 39 on page 109 g1 rxclk o, ts, id table 39 on page 109 g2 n/c ? table 39 on page 109 g3 txdata4 i, id table 39 on page 109 g4 gndd ? table 39 on page 109 g5 n/c ? table 39 on page 109 ball signal name type reference for full description
intel ? lxt9785 and intel ? lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 105 document number: 249241 revision number: 007 revision date: august 28, 2003 g6 gndd ? table 39 on page 109 g7 gndd ? table 39 on page 109 g8 gndd ? table 39 on page 109 g9 avss ? table 39 on page 109 g10 avss ? table 39 on page 109 g11 avss ? table 39 on page 109 g12 avcc ? table 39 on page 109 g13 tpin4 ai/ao table 39 on page 109 g14 tpip4 ai/ao table 39 on page 109 h1 n/c ? table 39 on page 109 h2 rxdata3_ss o, ts, id table 39 on page 109 h3 rxdata3_s o, ts table 39 on page 109 h4 vccio ? table 39 on page 109 h5 n/c ? table 39 on page 109 h6 gndd ? table 39 on page 109 h7 gndd ? table 39 on page 109 h8 gndd ? table 39 on page 109 h9 avss ? table 39 on page 109 h10 avss ? table 39 on page 109 h11 avss ? table 39 on page 109 h12 avcc ? table 39 on page 109 h13 tpin3 ai/ao table 39 on page 109 h14 tpip3 ai/ao table 39 on page 109 j1 txdata3 i, id table 39 on page 109 ball signal name type reference for full description j2 rxdata2_ss o, ts, id table 39 on page 109 j3 txclk i, id table 39 on page 109 j4 n/c ? table 39 on page 109 j5 gndd ? table 39 on page 109 j6 gndd ? table 39 on page 109 j7 gndd ? table 39 on page 109 j8 gndd ? table 39 on page 109 j9 avss ? table 39 on page 109 j10 avss ? table 39 on page 109 j11 avss ? table 39 on page 109 j12 avcc ? table 39 on page 109 j13 tpon3 ao/ai table 39 on page 109 j14 tpop3 ao/ai table 39 on page 109 k1 sync/ txsync i, id table 39 on page 109 k2 rxdata2_s o, ts table 39 on page 109 k3 txdata2 i, id table 39 on page 109 k4 n/c ? table 39 on page 109 k5 gndd ? table 39 on page 109 k6 gndd ? table 39 on page 109 k7 n/c ? table 39 on page 109 k8 amdix_en i, st, ip table 39 on page 109 k9 gndd ? table 39 on page 109 k10 gndd ? table 39 on page 109 k11 avss ? table 39 on page 109 ball signal name type reference for full description
106 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 intel ? lxt9785 and intel ? lxt9785e advanced 8-port 10/100 mbps phy transceivers k12 avcc ? table 39 on page 109 k13 tpop2 ao/ai table 39 on page 109 k14 tpon2 ao/ai table 39 on page 109 l1 n/c ? table 39 on page 109 l2 gndd ? table 39 on page 109 l3 vccio ? table 39 on page 109 l4 refclk0 i table 39 on page 109 l5 vccio ? table 39 on page 109 l6 n/c ? table 39 on page 109 l7 vccd ? table 39 on page 109 l8 n/c ? table 39 on page 109 l9 cfg_2 i, st, id table 39 on page 109 l10 n/c ? table 39 on page 109 l11 avss ? table 39 on page 109 l12 avcc ? table 39 on page 109 l13 tpip2 ai/ao table 39 on page 109 l14 tpin2 ai/ao table 39 on page 109 m1 rxdata1_ss o, ts, id table 39 on page 109 m2 rxdata1_s o, ts table 39 on page 109 m3 rxdata0_ss o, ts, id table 39 on page 109 m4 n/c ? table 39 on page 109 m5 n/c ? table 39 on page 109 m6 n/c ? table 39 on page 109 m7 n/c ? table 39 on page 109 ball signal name type reference for full description m8 n/c ? table 39 on page 109 m9 cfg_3 i, st, id table 39 on page 109 m10 cfg_1 i, st, id table 39 on page 109 m11 txslew_0 i, st, id table 39 on page 109 m12 txslew_1 i,st, id table 39 on page 109 m13 tpin1 ai/ao table 39 on page 109 m14 tpip1 ai/ao table 39 on page 109 n1 gndd ? table 39 on page 109 n2 txdata1 i, id table 39 on page 109 n3 rxdata0_s o, ts table 39 on page 109 n4 txdata0 i, id table 39 on page 109 n5 mdio io, ts, sl, ip table 39 on page 109 n6 led3_2 od, ts, sl, ip table 39 on page 109 n7 led2_2 od, ts, sl, ip table 39 on page 109 n8 led1_1 od, ts, sl, ip table 39 on page 109 n9 led0_1 od, ts, sl, ip table 39 on page 109 n10 add_4 i, st, id table 39 on page 109 n11 gndd ? table 39 on page 109 n12 tpin0 ai/ao table 39 on page 109 n13 tpon0 ao/ai table 39 on page 109 n14 tpop1 ao/ai table 39 on page 109 p1 gndd ? table 39 on page 109 ball signal name type reference for full description
intel ? lxt9785 and intel ? lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 107 document number: 249241 revision number: 007 revision date: august 28, 2003 p2 n/c ? table 39 on page 109 p3 n/c ? table 39 on page 109 p4 mdc i, st, id table 39 on page 109 p5 mdint od, ts, sl, ip table 39 on page 109 p6 led3_1 od, ts, sl, ip table 39 on page 109 p7 led2_1 od, ts, sl, ip table 39 on page 109 p8 led1_2 od, ts, sl, ip table 39 on page 109 p9 led0_2 od, ts, sl, ip table 39 on page 109 p10 add_3 i, st, id table 39 on page 109 p11 gndd ? table 39 on page 109 p12 tpip0 ai/ao table 39 on page 109 p13 tpop0 ao/ai table 39 on page 109 p14 tpon1 ao/ai table 39 on page 109 ball signal name type reference for full description
108 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 intel ? lxt9785 and intel ? lxt9785e advanced 8-port 10/100 mbps phy transceivers
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 109 document number: 249241 revision number: 007 revision date: august 28, 2003 3.6 bga15 signal descriptions 3.6.1 signal name conventions signal names may contain either a port designation or a serial designation, or a combination of the two designations. signal naming conventions are as follows: ? port number only. individual signals that apply to a particular port are designated by the signal mnemonic, immediately followed by the port designa tion. for example, transmit enable signals would be identifi ed as txen0, txen1, and txen2. ? serial number only. a set of signals which are not tied to any specific port are designated by the signal mnemonic, followed by an underscore and a serial designation. for example, a set of three global configuration signals would be identified as cfg_1, cfg_2, and cfg_3. ? port and serial number. in cases where each port is assi gned a set of multiple signals, each signal is designated in the following order: signal mnemonic, port designation, an underscore, and the serial designation. for exampl e, a set of three port configuration signals would be identified as rxdata0_0 and rxdata0_1, rxdata1_0 and rxdata1_1, and rxdata2_0 and rxdata2_1. 3.6.2 signal descriptions ? sm ii and ss-smii configurations table 39 provides the bga15 signal descriptions. table 39. intel ? lxt9785 bga15 signal descriptions (sheet 1 of 7) bga15 ball designation symbol type signal description smii/ss-smii common signal descriptions n4, n2, k3, j1, g3, e2, d3, a5 txdata0 txdata1 txdata2 txdata3 txdata4 txdata5 txdata6 txdata7 i, id transmit data - ports 0-7. these serial input streams provide data to be transmitted to the network. the lxt9785/9785e clocks the data in synchronously to refclk. c3 l4 refclk1 refclk0 i reference clock. the lxt9785/9785e always requires a 125 mhz reference clock input. refer to section 4.4.2, ?clock/sync requirements? on page 125 for detailed clock requirements. smii specific signal descriptions k1 sync i, id smii synchronization. the mac must generate a sync pulse every 10 refclk cycles to synchronize the smii. 1. type column coding: i = input, o = output, od = o pen drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull- down.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 110 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 n3, m2, k2, h3, f2, e3, b4, c5 rxdata0_s rxdata1_s rxdata2_s rxdata3_s rxdata4_s rxdata5_s rxdata6_s rxdata7_s o, ts receive data - ports 0-7 . these serial output streams provide data received from the network. the lxt9785/9785e drives the data out synchronously to refclk. ss-smii specific signal descriptions k1 txsync i, id ss-smii transmit synchronization. the mac must generate a txsync pulse every 10 txclk cycles to mark the start of txdata segments. e1 rxsync o, ts, id ss-smii receive synchronization. the lxt9785/9785e generates these pulses every 10 rxclk cycles to mark the start of rxdata segments for the mac. j3 txclk i, id ss-smii transmit clock. the mac sources this 125 mhz clock as the timing reference for txdata and txsync. see ?clock/sync requirements? on page 125 for detailed clock requirements. g1 rxclk o, ts, id ss-smii receive clock. the lxt9785/9785e generates these clocks, based on refclk, to provide a timing reference for rxdata and rxsync to the mac. see ?clock/sync requirements? on page 125 for detailed clock requirements . these outputs are only enabled when ss-smii mode is enabled. m3, m1, j2, h2, f3, c2, a4, c6 rxdata0_ss rxdata1_ss rxdata2_ss rxdata3_ss rxdata4_ss rxdata5_ss rxdata6_ss rxdata7_ss o, ts, id receive data - ports 0-7. these serial output streams provide data received from the network. the lxt9785/9785e drives the data out synchronously to refclk. mdio control interface signal descriptions n5 mdio i/o, ts, sl, ip management data input/output. bidirectional serial data channel for communication between the phy and mac or switch asic. refer to figure 21 on page 140 . p5 mdint od, ts, sl, ip management data interrupt. when register bit 18.1 = 1, an active low output on this pin indicates status change. refer to figure 21 on page 140 . table 39. intel ? lxt9785 bga15 signal descriptions (sheet 2 of 7) bga15 ball designation symbol type signal description 1. type column coding: i = input, o = output, od = open drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull- down.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 111 document number: 249241 revision number: 007 revision date: august 28, 2003 p4 mdc i, st, id management data clock. clock for the mdio serial data channel. maximum frequency is 20 mhz. only m dc0 is used when 1x8 port sectionalization is selected. in 2x4 port sectionalization mode, mdc0 clocks ports 0-3 register accesses and mdc1 clocks ports 4-7 register accesses. refer to figure 21 on page 140 . network interface signal description p13, n13, n14, p14, k13, k14, j14, j13, f14, f13, e13, e14, b14, a14, a13, b13 tpop0, tpon0 tpop1, tpon1 tpop2, tpon2 tpop3, tpon3 tpop4, tpon4 tpop5, tpon5 tpop6, tpon6 tpop7, tpon7 ao/ai twisted-pair outputs 2 , positive & negative, ports 0-7. during 100base-tx or 10base-t operation, tpo pins drive 802.3 compliant pulses onto the line. p12, n12, m14, m13, l13, l14, h14, h13, g14, g13, d13, d14, c14, c13, a12, b12 tpip0, tpin0 tpip1, tpin1 tpip2, tpin2 tpip3, tpin3 tpip4, tpin4 tpip5, tpin5 tpip6, tpin6 tpip7, tpin7 ai/ao twisted-pair inputs 3 , positive & negative, ports 0-7. during 100base-tx or 10base-t operation, tpi pins receive differential 100base-tx or 10base-t signals from the line. jtag test signal description c12 tdi i, st, ip test data input. test data sampled with respect to the rising edge of tck. c11 tdo o, ts test data output. test data driven with respect to the falling edge of tck. b11 tms i, st, ip test mode select. a11 tck i, st, id test clock. clock input for jtag test. a10 trst i, st, ip test reset. reset input for jtag test. miscellaneous signal description table 39. intel ? lxt9785 bga15 signal descriptions (sheet 3 of 7) bga15 ball designation symbol type signal description 1. type column coding: i = input, o = output, od = o pen drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull- down.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 112 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 m11, m12 txslew_0 txslew_1 i, st, id tx output slew controls 0 and 1 defaults. these pins are read at startup or reset. their value at that time is used to set the default state of register bits 27.11:10 for all ports. these register bits can be read and overwritten after startup / reset. these pins select the tx output slew rate for all ports (rise and fall time) as follows: txslew_1 txslew_0 slew rate (rise and fall time) 0 0 3.3 ns 0 1 3.6 ns 1 0 3.9 ns 1 1 4.2 ns c10 reset i, st, ip reset. this active low input is ored with the control register reset register bit 0.15. when held low, all outputs are forced to inactive state. pin is not on jtag chain. n10, p10 add_4 add_3 i, st, id address <4:3>. sets base address to one of the following four possible addresses: ? 00000 ? 01000 ? 10000 ? 11000 each port adds its port number (starting with 0) to this address to determine its phy address. port 0 address = base port 1 address = base + 1 port 2 address = base + 2 port 3 address = base + 3 port 4 address = base + 4 port 5 address = base + 5 port 6 address = base + 6 port 7 address = base + 7 e8 c9, modesel_1 modesel_0 i, st, id mode select[1:0]. 00 = reserved 01 = smii 10 = ss-smii 11 = reserved all ports are configured the same. interfaces cannot be mixed and must be all smii or ss-smii. table 39. intel ? lxt9785 bga15 signal descriptions (sheet 4 of 7) bga15 ball designation symbol type signal description 1. type column coding: i = input, o = output, od = open drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull- down.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 113 document number: 249241 revision number: 007 revision date: august 28, 2003 k8 amdix_en i, st, ip auto mdi/mdix enable default. this pin is read at startup or reset. its value at that time is used to set the default state of register bit 27.9 for all ports. these register bits can be read and overwritten after startup / reset. refer to table 40 on page 119 . when active (high), automatic mdi crossover (mdix) (regardless of segmentation) is selected for all ports. when inactive (low) mdix is select ed according to the mdix pin. m10, l9, m9 cfg_1 cfg_2 cfg_3 i, st, id global port configuration defaults 1-3. these pins are read at startup or reset. their value at that time is used to set the default state of register bits shown in table 42, ?intel? lxt9785/9785e global hardware configuration settings? on page 129 for all ports. these register bits can be read and overwritten after startup / reset. when operating in hardware control mode, these pins provide configuration control opt ions for all the ports (refer to page 129 for details). c1, f1 fifosel1 fifosel0 i, id, st fifo select <1:0>. these pins are read at startup or reset. their value at that time is used to set the default state of register bits 18.15:14 for all ports. these register bits can be read and overwritten after startup/reset. these pins are shared with rmii-rxer<5:4>. an external pull-up resistor (see applicati ons section for value) can be used to set fifo select<1:0> to active while rxer<5:4> are three-stated during hardware reset. if no pull-up is used, the default fifo select state is set via the internal pull-down resistors. see table 36, ?intel? lxt9785/lxt9785e receive fifo depth configurations? on page 97 . b3 linkhold i, id, st linkhold defaul t. this pin is read at startup or reset. its value at that time is used to set the default state of register bit 0.11 for all ports. this register bit can be read and overwritten after startup / reset. when high, the lxt9785/ 9785e powers down all ports. this pin is shared with rmii-rxer6. an external pull-up resistor (see applications section for value) can be used to set linkhold active while rxer6 is three-stated during h/w reset. if no pull-up is used, the default linkhold state is set inactive via t he internal pull-down resistor. led signal descriptions n9, p9 led0_1 led0_2 od, ts, sl, ip port 0 led drivers 1-2. these pins drive led indicators for port 0. each led can display one of several avail able status conditions as selected by the led configuration register (refer to table 96, ?led configuration register (address 20, hex 14)? on page 213 for details). table 39. intel ? lxt9785 bga15 signal descriptions (sheet 5 of 7) bga15 ball designation symbol type signal description 1. type column coding: i = input, o = output, od = o pen drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull- down.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 114 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 n8, p8 led1_1 led1_2 od, ts, sl, ip port 1 led drivers 1-2. these pins drive led indicators for port 1. each led can display one of several avail able status conditions as selected by the led configuration register (refer to table 96, ?led configuration register (address 20, hex 14)? on page 213 for details). p7, n7, led2_1 led2_2 od, ts, sl, ip port 2 led drivers 1-2. these pins drive led indicators for port 2. each led can display one of several avail able status conditions as selected by the led configuration register (refer to table 96, ?led configuration register (address 20, hex 14)? on page 213 for details). p6, n6 led3_1 led3_2 od, ts, sl, ip port 3 led drivers 1-2. these pins drive led indicators for port 3. each led can display one of several avail able status conditions as selected by the led configuration register (refer to table 96, ?led configuration register (address 20, hex 14)? on page 213 for details). b9, a9 led4_1 led4_2 od, ts, sl, ip port 4 led drivers 1-2. these pins drive led indicators for port 4. each led can display one of several avail able status conditions as selected by the led configuration register (refer to table 96, ?led configuration register (address 20, hex 14)? on page 213 for details). b8, a8 led5_1 led5_2 od, ts, sl, ip port 5 led drivers 1-2. these pins drive led indicators for port 5. each led can display one of several avail able status conditions as selected by the led configuration register (refer to table 96, ?led configuration register (address 20, hex 14)? on page 213 for details). a7, b7 led6_1 led6_2 od, ts, sl, ip port 6 led drivers 1-2. these pins drive led indicators for port 6. each led can display one of several avail able status conditions as selected by the led configuration register (refer to table 96, ?led configuration register (address 20, hex 14)? on page 213 for details). b6, a6 led7_1 led7_2 od, ts, sl, ip port 7 led drivers 1-2. these pins drive led indicators for port 7. each led can display one of several avail able status conditions as selected by the led configuration register (refer to table 96, ?led configuration register (address 20, hex 14)? on page 213 for details). power supply signal descriptions d12, e12, f12, g12, h12, j12, k12, l12, avcc ? analog power supply. +2.5 v supply for analog circuits. table 39. intel ? lxt9785 bga15 signal descriptions (sheet 6 of 7) bga15 ball designation symbol type signal description 1. type column coding: i = input, o = output, od = open drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull- down.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 115 document number: 249241 revision number: 007 revision date: august 28, 2003 e11, f9, f10, f11, g9, g10, g11, h9, h10, h11, j9, j10, j11, k11, l11 avss ? analog ground. ground return for analog supply (avcc). all grounds can be tied together using a single ground plane. d7, l7 vccd ? digital power supply - core. +2.5 v supply for core digital circuits. d4, f4, h4, l3, l5, vccio ? digital power supply - i/o ring. +2.5/3.3 v supply for digital i/o circuits. the digital input circuits running off of this rail, having a ttl-level threshold and over-voltage protection, may be interfaced with 3.3/5.0 v, when the io supply is 3.3 v, and 2.5/3.3/5.0 v when 2.5 v. a1, a2, a3, b1, b2, b5, b10, d9, d11, e5, e6, e9, e10, f5, f6, f7, f8, g4, g6, g7, g8, h6, h7, h8, j5, j6, j7, j8, k5, k6, k9, k10, l2, n1, n11, p1, p11 gndd ? digital ground. ground return for core digital supplies (vccd). all ground pins can be tied together using a single ground plane. c8 sgnd ? substrate ground. ground for chip substrate. all ground pins can be tied together using a single ground plane. unused/reserved balls c4, c7, d1, d2, d5, d6, d8, d10, e4, e7, g2, g5, h1, h5, j4, k4, k7, l1, l6, l8, l10, m4, m5, m6, m7, m8, p2, p3 n/c ? no connection. table 39. intel ? lxt9785 bga15 signal descriptions (sheet 7 of 7) bga15 ball designation symbol type signal description 1. type column coding: i = input, o = output, od = o pen drain output, st = schmitt triggered input, ts = three-state-able output, sl = slew-rate limited output, ip = weak internal pull-up, id = weak internal pull- down.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 116 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 4.0 functional description 4.1 introduction the intel ? lxt9785/lxt9785e is an 8-port fast ethern et 10/100 phy transceiver that supports 10 mbps and 100 mbps networks, complying with all applicable requirements of ieee 802.3 standards. the device incorpor ates a serial media indepe ndent interface (smii), source synchronous-serial media independent interface (ss-smii), and a reduced serial independent interface (rmii) to enable each individual networ k port to interf ace with multiple 10/100 macs. each port directly drives eith er a 100base-tx line or a 10base-t line. the lxt9785/9785e also supports 100base-fx operation via an lvpe cl interface. the device has a 241-ball bga, a 208-pin qfp, or a 196-ball bga package. the 196-ball bga package (bga15) is a reduced feature-set pr oduct. the bga15 package does not support the following features: ? rmii ? fiber ? sectionalization ? third led port (only two leds per port) ? hardware control pins: ?pause ?mdix ?mddis ?pwrdwn ? lower three phy address (out of five phy address bits) ? extended temperature note: unless otherwise noted, all information in this document applies to the lxt9785 and lxt9785e. 4.1.1 osp? architecture the intel lxt9785/lxt9785e incorporates high -efficiency optimal signal processing? design techniques, combining the best prop erties of digital and analog signal processing to produce a truly optimal device. the receiver utilizes decision f eedback equalization to increase no ise and cross-talk immunity by as much as 3 db over an ideal all-analog equali zer. using osp mixed-signal processing techniques in the receive equalizer avoids the quantization noise and calculation truncation errors found in traditional dsp-based receivers (t ypically complex dsp engines wi th a/d converters). the result is improved receiver noise and cross-talk performance. the osp architecture also requir es substantially less computational logic than traditional dsp- based designs. the result is lower power consumption and reduced logic switching noise generated by dsp engines clocked at speeds up to 125 mhz. the logic switching noise can be a considerable source of emi when generated from the device?s power supplies.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 117 document number: 249241 revision number: 007 revision date: august 28, 2003 the osp-based lxt9785/lxt9785e provides improved data recovery, emi performance and power consumption. 4.1.2 comprehensive functionality the lxt9785/lxt9785e performs all functions of the physical coding sublayer (pcs) and physical media attachment (pma) sublayer as defined in the ieee 802.3 100base-x specification. this device also performs all functions of the physical media dependent (pmd) sublayer for 100base-tx connections. on power-up, the lxt9785/lxt9785e reads its conf iguration inputs to check for forced operation settings. if not configured for for ced operation, each port uses auto -negotiation/parallel detection to automatically determine line operating conditions. if the phy device on the other side of the link supports auto-negotiation, the lxt9785/lxt9785e auto-negotiates with it using fast link pulse (flp) bursts. if the phy partner does not s upport auto-negotiation, the lxt9785/lxt9785e automatically detects the presence of either link pul ses (10 mbps phy) or idle symbols (100 mbps phy) and set its operatin g conditions accordingly. the lxt9785/lxt9785e provides half-duplex a nd full-duplex operation at 100 mbps and 10 mbps. 4.1.2.1 sectionalization the lxt9785/lxt9785e?s sectional design allows flexibility with large multiport macs and asics. with the use of the section pin, the lxt9785/lxt9785e can be configured into a single 8- port or two separate 4-port sections, each with it s own mdio (with separate mdc clock) and mii data (with separate refclk/txclk/rxclk clocks) interfaces. see figure 16, ?intel? lxt9785/lxt9785e typical smii quad sectionalization diagram? on page 134 , figure 21, ?intel? lxt9785/lxt9785e typical ss-smii quad sectionalization diagram? on page 140, and figure 26, ?intel? lxt9785/lxt9785e typical rmii quad sectionalization diagram? on page 144 . note: the bga15 package does no t support sectionalization. 4.2 interface descriptions 4.2.1 10/100 network interface the lxt9785/lxt9785e supports 10 mbps and 100 mbps (10base-t and 100base-tx) ethernet over twisted-pair, or 100 mbps (100base -fx) ethernet over fiber media. each network interface port consists of four external pins (two differential signal pair s). the pins are shared between twisted-pair (tp) and fiber. the lxt9 785/lxt9785e pinout is designed to interface seamlessly with dual-high stacked rj-45 connectors. refer to table 11, ?intel? lxt9785/ lxt9785e netw ork interface signal descriptions ? pqfp? on page 42 for specific pin assignments. the lxt9785/lxt9785e output drivers generate either 100base-tx, 10base-t, or 100base- fx output. when not transmitting data, the devi ce generates ieee 802.3-compliant link pulses or idle code. input signals are decoded either as a 100base-tx, 100base-fx, or 10base-t input, depending on the mode selected. auto-negotiation/parallel detection or manual control is used to determine the speed of this interface.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 118 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 4.2.1.1 twisted-pair interface the lxt9785/lxt9785e supports either 100ba se-tx or 10base-t connections over 100 ?, category 5, unshielded twisted-pair (utp). only a transformer, rj-45, and bypass capacitors are required to complete this interface. using intel's patented wa veshaping technology, the transmitter shapes the outgoing signal to help reduce the need for external emi filters. four slew rate settings (refer to table 13, ?intel? lxt9785/lxt9785e miscellaneous signal descriptions ? pqfp? on page 43 ) allow the designer to match the output wa veform to the magnetic characteristics. both transmit and receive terminations are built into the lxt9785/lxt9785e so no external components are required betw een the lxt9785/lxt9785e and th e external transformer. the transmitter uses a transformer with a center tap to help reduce power consumption. when operating at 100 m bps, mlt3 symbols are c ontinuously tran smitted and received. when not transmitting data, the lxt9785/lxt9785e generates ?idle? symbols. figure 7. intel ? lxt9785/lxt9785e interfaces txen n rxd n_0 txd n_0 txd n_1 rxd n_1 crs_dv n rxer n data interface mddis mdcn mdintn mdion mdio management interface led n_ 2 led n _3 port leds/ controls add<4:0> tpfop n tpfon n tpfip n tpfin n network interface vccio +3.3 v or +2.5 v vccd +2.5 v gndd .01 uf addr & mdix/ contr mode select mdix_enb direct drive txclk rxclk led n_ 2
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 119 document number: 249241 revision number: 007 revision date: august 28, 2003 during 10 mbps operation, lxt9785/lxt9785e encoded data is exchanged. when no data are being exchanged, the line is left in an idle state with nlps transmitted to maintain link. 4.2.1.2 mdi crossover (mdix) the lxt9785/lxt9785e crossover function, which is compliant to the ieee 802.3, clause 23 standard, connects the transmit output of the device to the far-end receiver in a link segment. this function can be disabled via register bits 27.9:8 or by using the hardware configuration pins. note: the bga15 package does not support mdix hardware configuration. software must be used to control the function after power-up. 4.2.1.3 fiber interface the lxt9785/lxt9 785e fiber ports are design ed to interface with comm on industry-s tandard 3.3 v and 5 v fiber-optic tran sceivers. each of the 8 ports incor porates a low-voltage pecl interface that complies with the ansi x3.166 standard for seamless integration. note: the bga15 package does not support the fiber interface. fiber mode is selected through register bit 16.0 by the following two methods: 1. configure register bit 16.0 = 1 on a global ba sis (all 8 ports) by driving the hardware control pin g_fx/tp to a logic high value on power-up and/or reset. 2. configure register bit 16.0 = 1 on a pe r-port basis through the mdio interface. the fiber interface is capable of full-duplex or ha lf-duplex operation. in half duplex, operation collisions must be managed by external layer 2 logi c (mac). auto negotiation is not supported for fiber mode. 4.3 media independent in terface (mii) interfaces the lxt9785/lxt9785e supports reduced mii or se rial mii, but not concurrently. the interface mode selection pins configures the device for either rmii or sm ii/ss-smii on all eight ports. refer to table 41 for the mode select settings. note: the bga15 package does not support the rmii interface. 4.3.1 global mii mode select the mode select pins are used for mii interface configuration sett ings upon power-up sequencing. all ports are configur ed the same and can not be intermixed. table 40. intel ? lxt9785/lxt9785e mdix selection amdix_en mdix mdix mode 0 0 mdi forced 0 1 mdix forced 1 x auto mdi/mdix
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 120 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 4.3.2 internal loopback register bit 0.14 must be set to enable internal loopback operation. register bits 16.14 and 0.8 must be set for 10 mbps operation. intel recomm ends that auto-negotia tion be disabled while internal loopback is enabled. the normal auto-n egotiation process code wo rd exchange cannot be completed.the following two-step sequence is r ecommended for the most efficient mode change when enabling forced 100 mbps internal loopback mode directly from auto-negotiation mode: 1. write register 0 with 0x2100h (forced 100 mbps), and 2. write register 0 with 0x6100h (enable internal loopback with forced 100 mbps) this two-step process ensures the 100 mbps link comes up quickly. if the one-write process of writing 0x6100h is followed, it may take up to 1.5 seconds before link is established and data is received on the port. the 1.5 second delay is du e to the ieee auto-negot iation break link timer (blt) requirement. the timer must expire before link is established when changing modes directly from auto-negotiation to internal loopback forced 100 mbps mode. use the above two-step process to eliminate the auto-negotiation blt timer requirement. 4.3.3 rmii data interface the lxt9785/lxt9785e provides a separate rm ii for each network port, each complying with the rmii specification, revision 1.2. the rmii includes both a data interface and an mdio management interface. the rmii data interface exchanges data between the lxt9785/lxt9785e and up to eight media access controllers (macs). table 41. intel ? lxt9785/lxt9785e mii mode select modesel1 modesel0 rmii 1 00 smii 0 1 ss-smii 1 0 reserved 1 1 1. invalid for the bga15 package. figure 8. intel ? lxt9785/lxt9785e internal loopback loopback digital block analog block rmii/ smii/ ss- smii inter face fx driver tx driver lxt9785/9785e
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 121 document number: 249241 revision number: 007 revision date: august 28, 2003 4.3.4 serial media independent interf ace (smii) and source synchronous- serial media independent interface (ss-smii) 4.3.4.1 smii interface the lxt9785/lx t9785e provides an independent serial inte rface for each network port, complying with the serial-mii sp ecification, revision 1.2. all smii ports use a common reference clock and sync signal. the smii data in terface exchanges data between the lxt9785/ lxt9785e and multiple media a ccess controllers (macs). all signals are synchronous to the reference clock. one sync control stream is s ourced by the mac to the ph y. both the transmit and receive data streams are segmented into boundaries delimited by the sync pulses. this interface is expected to drive up to 6 inches of trace lengths. 4.3.4.2 source synchronous- serial media independent interface the new revision to the smii interface, ss-smii, allows for a longer trace length and helps to relieve timing constraints, requiring the addition of four new signals, txclk, txsync, rxclk, and rxsync. the transmit txclk and txsync are sourced from the mac to the phy and referenced to the refclk input . the receive rxclk and rxsync are sourced by the phy to the mac and in reference to the refclk. 4.3.5 configuration management interface the lxt9785/lx t9785e provides an mdio management interf ace and a hardware control interface (via the cfg pins) for device configurat ion and management. mode control selection is provided via the mddis pin as shown in table 9, ?intel? lxt9785/lxt9785e mdio control interface signals ? pqfp? on page 41 . when sectionalization (2x4) is selected, separate mdio interfaces are enabled (see figure 13 on page 127 ). 4.3.6 mii isolate in applications where the mii must be isolated from the bus, the rmii and the smii/ss-smii configurations can be three-stated using register 0.10. on each individual port, register bit 0.10 controls the isolation of the transm it and receive data signals for that port. register bit 0.10 on ports 0 and 4 isolate the rxclk n /txclk n and sync signals. when 1x8 sectionalization is selected, txclk0 , txsync0, rxclk1, and rxsync1 are used for the clocking and synchronization interface. port 4 controls the isolation of rxclk0, rxclk1, rxsync0, and rxsync1, and must be used to isolate the receive cloc k and synchronization interface. when 2x4 sectionalization is selected, txclk0 , txsnc0, rxclk0, and txclk0 are used for port 0 through port 3 and txclk1, txsync1, rxclk1, and rxsync1 are used for port 4 through port 7. port 0 must be isolated to isol ate the receive clock and synchronization interface for port 0 through port 3. port 4 must be isolated to isolate port 4 through port 7. 4.3.7 mdio management interface the lxt9785/lxt9785e supports the ieee 802.3 mii management interface, also known as the management data input/output (mdio) interface. this interface allows upper-layer devices to monitor and control the state of the lxt9785/lxt9 785e. the mdio inte rface consists of a
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 122 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 physical connection, a specific pr otocol that runs across the conn ection, and an internal set of addressable registers. some registers are requ ired and their functions are defined by the ieee 802.3 specification. additional registers allow for expanded functionality. specific bits in the registers are referenced using an ?x.y? notation, where x is the register number (0-32) and y is the bit number (0-15). the physical interface consists of a data line (m dio) and clock line (mdc). operation of this interface is controlled by the mddis input pi n. when mddis is high, all the mdios are completely disabled. the hardware control in terface provides primary co nfiguration control. when mddis is low, the mdio port is enable d for both read and write operations and the hardware control interface is not used. note: the bga15 package does not support the mddis pin. the timing for the mdio interface is shown in table 79, ?intel? lxt9785/lxt9785e mdio timing parameters? on page 197 . mdio read and writ e cycles are shown in figure 9, ?intel? lxt9785/lxt9785e management interface read frame structure? on page 122 and figure 10, ?intel? lxt9785/lxt9785e ma nagement interface write frame structure? on page 122 . the protocol allows one controller to communi cate with multiple lxt9785/lxt9785e chips. pins add_<4:0> determine the base addr ess. each port adds its port nu mber to the base address to obtain its port address as shown in figure 11 . the bga15 package uses a similar scheme where the add_[2:0] bits internally set to 0 and the add_[4:3] bits are used to select from four base addresses (0x00000b, 0x01000b, 0x10000b, or 0x11000b. figure 9. intel ? lxt9785/lxt9785e management interface read frame structure figure 10. intel ? lxt9785/lxt9785e management interface write frame structure mdc mdio (read) 32 "1"s 0110 preamble st op code phy address turn around z0 a4 a3 a0 r4 r3 r0 register address d15 d14 d1 data write read d15 d14 d1 d0 idle high z mdc mdio (write) 32 "1"s 0101 preamble st op code phy address turn around 1 0 a4 a3 a0 r4 r3 r0 register address d15 d14 d1 d0 data idle idle write
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 123 document number: 249241 revision number: 007 revision date: august 28, 2003 4.3.8 mii sectionalization when sectionalized into two quad sections, the mdio bus splits into two separate phy access ports. ports 0-3 of the mdio sect ion operate independently of ports 4-7. the mii isolate function is unaffected and operates normal ly. sectionalization is selected by pulling pin 176 (section) high on the initial power-up sequence (refer to figure 13 ). in applications that need sectionalization, such as 1x8 and 2x4 and have a single mdio bus structure, it is necessary that the addressing scheme be contiguous. for example, the first eight ports are addressed 0-7, so the next four ports must be addressed 8-11. note: the bga15 package does not suppor t the mii sectionalization feature. 4.3.9 mii interrupts the lxt9785/lxt9785e provides a single per-section interrupt pin that is available to all ports. interrupt logic is shown in figure 12 . the lxt9785/lxt9785e also provides two dedicated interrupt registers for each port. register 18 provides interrupt enable and mask functions and register 19 provides interrupt status. setting re gister bit 18.1 = 1 enables a port to request interrupt via the mdint pin. an active low on this pin indi cates a status change on the device. because it is a shared interrupt, there is no indication which port is requesting interrupt service (see figure 12 ). there are five conditions th at may cause an interrupt: figure 11. intel ? lxt9785/lxt9785e port address scheme ba se add _< 4:0> (example add_<4:0> = 4) phy add_<4:0> (base+0) phy add_<4:0> (base+1) phy add_<4:0> (base+2) phy add_<4:0> (base+3) phy add_<4:0> (base+4) phy add_<4:0> (base+5) e x. 4 e x. 5 e x. 6 e x. 7 e x. 8 e x. 9 lxt9785 por t 0 por t 1 por t 2 port 3 port 4 port 5 phy add_<4:0> (base+7) ex. 11 por t 7 phy add_<4:0> (base+6) ex. 10 port 6 lxt9785/9785e
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 124 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 ? auto-negotiation complete. ? speed status change. ? duplex status change. ? link status change. ? isolate status change. 4.3.10 global hardware control interface the lxt9785/lxt9785e provides a hardware co ntrol interface for applications where the mdio is not desired. refer to ?initialization? on page 126 for additional details. 4.3.11 fifo initial fill values the fifo initial fill value sets the number of bits required to be written into the fifo before the process of reading the packet out of the fifo is started. the read operation is aligned on nibble boundaries because the fifo is one nibble wide. the read clock on the rm ii and smii interfaces may occur any time within the next available nibble. therefore, th e effective size of the fifo is one nibble less than the selected size. large initial fill fifo settings alter both the da ta-path latency and the interframe gap (ifg) output on the rmii and smii interfaces. the latency values are increased or decreased depending on the number of bits the fifo size is increased or decreased. the ifg may decrease up to twice the size of the initial fill fifo setting. when the follow ing three conditions are me t, the ipg on the rmii and smii interfaces may become nonexistent be tween packets, effectiv ely concatenating the packets into one long corrupted packet: ? the frequency difference between the link pa rtner and the local lxt9895 device exceed 200 ppm (the ieee standard requirement). ? jumbo packets (8192 byte pack ets or longer) are used. ? packets on the wire occur w ith minimum inter-packet gap (ipg) of 96 bit times. the concatenation of the packets is flagged by the mac as a crc er ror and possibly an oversized packet depending upon the length indication capabilities of the mac. the possibility of packet concatenation can be minimized on the rmii interf ace by setting the initial fill fifo register bits 18.15:14 to 01. the fifo setting bits shou ld be set to 10 for the smii interfaces. figure 12. intel ? lxt9785/lxt9785e interrupt logic force interrupt interrupt enable event x enable reg event x status reg interrupt pin . . . and or and . . . per port per event por t combine logic interrupt (event) status register is cleared on read. x = any int errupt capabi lity
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 125 document number: 249241 revision number: 007 revision date: august 28, 2003 4.4 operating requirements 4.4.1 power requirements the lxt9785/lxt9785e requires four power supply inputs: vccd , vcca, vccpecl and vccio. the digital and analog circuits require 2.5 v supplies (vccd, vccr, and vcct). these inputs may be supplied from a single source al though decoupling is requ ired to each respective ground. the fiber vccpecl supply can be connected to either 2.5 v or 3.3 v. a separate power supply may be used for the mii, jtag and mdio (vccio) interfaces. the power supply may be either +2.5 v or +3.3 v. vccio should be supplied from the same power source used to supply the controller on th e other side of the interface. refer to table 53, ?intel? lxt9785/lxt9785e digital i/o dc electrical characteristics (vccio = 2.5 v +/- 5%)? on page 174, table 54, ?intel? lxt9785/lxt9785e di gital i/o dc electrical characteristics (vccio = 3.3 v +/- 5%)? on page 175, and table 55, ?intel? lxt9785/lxt9785e digital i/o dc electrical characteristi cs ? sd pins? on page 175 for i/o characteristics. as a matter of good practice, these supplies should be as clean as possible. typical filtering and decoupling are shown in figure 34 on page 168 . the power supplies should be brought up as close to the same time as possible. however, there are no specific timing requirements. 4.4.2 clock/sync requirements 4.4.2.1 reference clock the lxt9785/lxt9785e requires a constant en abled reference clock (refclk). refclk?s frequency must be 50 mhz for rmii or 125 mhz for smii/ss-smii. the reference clock is used to generate transmit signals a nd recover receive signals. a crystal-based clock is recommended over a derived clock (that is, pll-based) to minimize transmit jitter. refer to table 56, ?intel? lxt9785/lxt9785e required clock characteristics? on page 175 for clock timing requirements. for applications that use a single 8-port sectionalization, refclk0 and refclk1 must always be tied together and to the source. in 2x4 applications, refclk0 and refclk1 are not tied together. 4.4.2.2 txclk signal (ss-smii only) the lxt9785/lxt9785e requires a 125 mhz input transmit clock synchronous with txdata n and frequency locked to refclk . see figure 22 on page 141. 4.4.2.3 txsync signal (smii/ss-smii) the lxt9785/lxt9785e requires a 12.5 mhz input pulse for smii synchronization. see figure 22 on page 141. 4.4.2.4 rxsync signal (ss-smii only) the lxt9785/lxt9785e provides a 12.5 mhz ou tput pulse synchronous with the rxdata n outputs. see figure 23 on page 141.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 126 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 4.4.2.5 rxclk signal (ss-smii only) in ss-smii mode, the lxt9785/lxt9785e provides a 125 mhz clock output in reference to the output rxdata n . rxclk is referenced and s ynchronized to the refclk. see figure 23 on page 141. 4.5 initialization when the lxt9785/lxt9785e is first powered on, re set, or encounters a li nk failure state, it checks the mdio register configuration bits to determine the line speed and operating conditions to use for the network link. the configuration bi ts may be set by the hardware control or mdio interface as shown in figure 13 on page 127 . 4.5.1 mdio control mode in the mdio control mo de, the lxt9785/lx t9785e reads the ha rdware control interface pins to set the initial (default) values of the mdio regist ers. once the initial values are set, bit control reverts to the mdio interface. 4.5.2 hardware control mode in the hardware control mode, the lxt9785/lxt97 85e disables direct write operations to the mdio registers via the mdio interface. on pow er-up or hardware reset, the lxt9785/lxt9785e reads the hardware control interface pins and sets the mdio registers accordingly. the following modes are available using e ither hardware control or mdio control: ? force network link to 100base-fx (fiber). ? force network link operation to: ? 100base-tx, full-duplex ? 100base-tx, half-duplex ? 10base-t, full-duplex ? 10base-t, half-duplex ? allow auto-negotiation/parallel-detection. ? auto/manual mdix enable/disable. ? pause for full-duplex links operation. ? global output slew rate control. when the network link is forced to a specific configuration, the lxt9785/lxt9785e immediately begins operating the network interface as commande d. when auto-negotia tion is enabled, the lxt9785/lxt9785e begins the auto-negotiation/ parallel-detection operation.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 127 document number: 249241 revision number: 007 revision date: august 28, 2003 4.5.3 power-down mode the lxt9785/lxt9785e incorporates numerous features to maintain the lowest power possible. the device can be put into a low-pow er state via register 0 as well as a near-zero power state with the power down pin. when in power-down mode, the device is not capable of receiving or transmitting packets. the lowest power operation is achieved using the global power-down pin, which is active high. this pin powers down every circuit in the device, including all clocks. all registers are unaltered and maintained when the global pwrdwn pin is released. note: the bga15 package does not s upport the pwrdwn pin feature. individual ports (software power down) can be powered down using register bit 0.11. this bit powers down a significant portion of the port, but cloc ks to the register section remain active. this allows the management interface to remain act ive during register power-down. the power-down bit is active high. figure 13. intel ? lxt9785/lxt9785e initialization sequence mddis voltage level? high low mdio control mode hardware control mode disable mdio writes reset mdio registers to values read at h/w control interface at last hardware reset pass control to mdio interface power-up or reset initialize mdio registers read h/w control interface hardware reset? software reset? yes yes
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 128 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 note: intel recommends that a minimum r ecovery time be allowed after bringing up a port from software or hardware power-down or link hold-off modes. the recovery times are specified in table 80, ?intel? lxt9785/lxt9785e power-up timing parameters? on page 198 4.5.3.1 global (hardware) power down the global power-down mode is controlled by the pwrdwn pin. when pwrdwn is high, the following conditions are true: ? all lxt9785/lxt9785e ports and the clock are shut down. ? all outputs are three-stated. ? all weak pad pull-up and pull-down resistors are disabled. ? the mdio registers are not accessible. ? configuration pins are read upon release of the pwrdwn pin, and registers are loaded with the current values of the ha rdware configuration pins. 4.5.3.2 port (software) power down individual port power-down control is provided by register bit 0.11 in the respective port control registers (refer to table 83, ?control register (address 0)? on page 200 ). during individual port power-down, the following conditions are true: ? the individual port is shut down. ? the mdio registers remain accessible. ? pull-up and pull-down resisters are not aff ected and the outputs are not three-stated. ? the register remains unchanged. 4.5.4 reset the lxt9785/lxt9785e provides both hardware and software resets. configuration control of auto-negotiation, speed, and dupl ex mode selection is handled differently for each. during a hardware reset, settings for bits 0.13, 0.12, 0.8, and 4.8:5 are read in from the pins (refer to table 42, ?intel? lxt9785/9785e global hard ware configuration settings? on page 129 for pin settings, and table 83, ?control register (address 0)? on page 200 and table 87, ?auto- negotiation advertisement regi ster (address 4)? on page 204 for register bit definitions). during a software reset (register bit 0.15 = 1), the bit settings are not re-read from the pins and revert back to the values that we re read in during the last hardware reset. any changes to pin values from the last hardware reset are no t detected during a software reset. during a hardware reset, register information is una vailable for 1 ms after de-assertion of the reset. all mii interface pins are disabled during a hardware reset and re leased to the bus on de-assertion of reset. during a software reset (0.15 = 1) the registers are available for reading. the reset bit should be polled to see when the part has completed reset (0.15 = 0). pull up and pull down resisters are not affected.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 129 document number: 249241 revision number: 007 revision date: august 28, 2003 intel recommends that a minimum recovery time be allowed after bringing up a port from software or hardware reset. the reco very times are specified in table 80, ?intel? lxt9785/lxt9785e power-up timing parameters? on page 198 4.5.5 hardware configuration settings the lxt9785/lxt9785e provides a hardware option to set the initial device configuration. the hardware option uses three global cfg pins that provide control for all ports (see table 42 ). 4.6 link establishment 4.6.1 auto-negotiation the lxt9785/lxt9785e attempts to auto-negotiate with its link partner by sending fast link pulse (flp) bursts. each burst consis ts of 33 link pu lses spaced 62.5 s apart. odd link pulses (clock pulses) are always present. even link pulses (data pulses) may also be present or absent to indicate a ?1? or a ?0?. each flp burst exchanges 16 bits of data, referred to as a ?page?. all devices that support auto-negotiation must impl ement the ?base page?, defined by ieee 802.3 (registers 4 and 5). the lxt9785/lxt9785e also supports the optional ?next page? function (registers 7 and 8). 4.6.1.1 base page exchange by exchanging base pages, the lxt9785/lxt 9785e and its link partner communicate their capabilities to each other. both si des must receive at least three id entical base pages for negotiation to proceed. each side finds their highest common capabilities, exchange more pages, and agree on the operating state of the line. table 42. intel ? lxt9785/9785e global hardware configuration settings desired mode cfg pin settings 1 resulting register bit values autoneg speed duplex 1 2 3 0.12 0.13 0.8 4.8 4.7 4.6 4.5 disabled 10 half low low low 0 0 0 n/a auto-negotiation advertisement full low low high 1 100 half low high low 1 0 full low high high 1 enabled 100 half high low low 1 1001 00 full/half high low high 1 0 1 1 10/100 half high high low 1 0 0 1 0 1 full/half high high high 1 0 1 1 1 1 1. refer to table 5, ?intel? lxt9785/lxt9785e rmii si gnal descriptions ? pqfp? on page 36 through table 17, ?intel? lxt9785/lxt9785e receiv e fifo depth considerations? on page 50 table 24, ?intel? lxt9785/lxt9785e rmii signal desc riptions ? bga23? on page 82 through table 36, ?intel? lxt9785/ lxt9785e receive fifo depth configurations? on page 97 , and table 39, ?intel? lxt9785 bga15 signal descriptions? on page 109 for cfg pin assignments.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 130 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 4.6.1.2 manual next page exchange additional information, exceeding that required by base page exchange, is also sent via ?next pages.? the lxt9785/lxt9785e fully supports the ieee 802.3 method of negotiation via next page exchange. the next page exchange uses re gister 7 to send information and register 8 to receive it. next page exchange occurs only if both e nds of the link partners a dvertise their ability to exchange next pages. a special mode has been ad ded to make manual next page exchange easier for software. when register 6 ?page? is received, it stays set until read. this bit is cleared when a new negotiation occurs, preventing the user from reading an old value in register 6 and assuming there is valid inform ation in registers 5 and 8. the page received bit is cleared upon reading the ?auto-negotiation expansion regi ster (address 6)? on page 206 . 4.6.1.3 controlling auto-negotiation the following steps ar e recommended when auto-negotiatio n is controlled by software: ? after power-up, power-down, or reset, the power-down recovery ti me, as specified in table 80, ?intel? lxt9785/lxt9785e power-up timing parameters? on page 198 , must be exhausted before proceeding. ? set the auto-negotiation advertisement regi ster bits in register 4 as desired. ? enable auto-negotiation (set md io register bit 0.12 = 1). ? enable or restart auto-negotiation as soon as possible after writing to register 4 to ensure proper operation. 4.6.1.4 link criteria in 100 mbps mode, link is established when the descrambler becomes locked and remains locked for approximately 50 ms. link rema ins up unless the descrambler recei ves less than 12 consecutive idle symbols in any 2 ms period. this provides a robust operation, filtering out any small noise hits that may disrupt the link. mlt-3 idle waveforms, for short periods, meet al l the criteria for 10base-t start delimiters. a working 10base-t receive may te mporarily indicate lin k to 100base-tx waveforms. however, the phy will not bring up a permanent 10 mbps link. according to the ieee standard 10 mbps link stat e machine, the last condition that must be met before 10 mbps link can come up is a period of transmit and receive idle time. txen and rxdv are inactive at the same time. this ensures that link is not brought up in the middle of transmitting or receiving a packet. to ensure link establishment, intel recommends no packet transmission into the mii interface until link is established. the ieee standard references this requirement in section 14.2.3 state diagrams, figure 14-6-link integrity test function state diagram and in section 28.3.4 state diagrams, figure 28-17-nlp receive link integrity test state diagram. these diagrams illustrat e that while the phy is in the link test fail extend state, the last state before link pass state) packet receive activity (rd) and transmit activity (do) must be idle (rd = idle * d0 = idle) for link to establish.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 131 document number: 249241 revision number: 007 revision date: august 28, 2003 4.6.1.5 parallel detection in parallel with auto-negotiation, the lxt9785/lxt9785e also monitors for 10 mbps normal link pulses (nlp) or 100 mbps idle symbols. if either symbol is detected, the device automatically reverts to the corresponding operating speed in half-duplex mode. parallel detection allows the lxt9785/lxt9785e to communicate with devices that do not support auto- negotiation. when parallel detection resolves a link, the li nk must be established in half-duplex mode. according to ieee st andards, the forced link partner cannot be configured to full-duplex. if the auto-negotiation link partner does not advertise ha lf-duplex capab ility at the speed of the forced link partner, link is not established. the ieee standard prevents forced full-duplex-to-half-duplex link connections. 4.6.1.6 reliable link establishment while auto mdi/mdix is enabled in forced speed mode with auto mdi/mdix hardware en abled, end users experience reliab le link establishment under all settings of auto mdi/mdix and speed between the lxt9785/lxt9785e and its link partners. as stated in the ieee clauses 40.4.5 .1 (auto mdi/mdix) and 28.3.2 (p arallel detect), when ports are forced to 10 mbps or 100 mbps and auto mdi/mdix is enabled, and the port is connected to a partner with auto-negotiation enabled, an undefined condition exists between the ieee auto mdix and parallel detect specifications. link may not occur according to the ieee specification. during this undefined condition, when the lxt9785 /lxt9785e is set to 10 mbps or 100 mbps and auto mdi/mdix is enabled, the lxt9785/lxt9785e and the link partner auto-negotiation processes are expected to be skewed enough to es tablish link in all but the rarest cases. auto mdi/ mdix is configured through hardware and software. if auto mdi/mdix operation is desired in forced modes, disabling auto mdi/mdix using the software programming can aid link establishment. figure 14. intel ? lxt9785/lxt9785e auto-negotiation operation check value 0.12 start done enable auto-neg/parallel detection go to forced settings attempt auto- negotiation listen for 10t link pulses listen for 100tx idle symbols link set? no yes power-up, reset, link failure disable auto-negotiation 0.12 = 0 0.12 = 1
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 132 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 4.7 serial mii operation the lxt9785/lxt9785e exchanges tr ansmit and receive data with the controller via the serial mii (smii). the smii performs the following functions: ? conveys complete mii information between a 10/100 phy and mac with two pins per port. ? allows a multi-port mac/phy communication with one system clock. ? operates in both half and full-duplex. ? supports per-packet switching between 10 mbps and 100 mbps data rates. the serial mii operates at 125 mhz using a global reference clock and frame synchronization signal (refclk and sync). each port has an individual two-line data interface (txdata n and rxdata n ). all signals are synchronous to refclk. table 43 summarizes the smii signals. data is exchanged in 10-bit serial words. each word contains one data byte (two nibbles of 4b coded data) and two status bits. when the port is operating at 10 0 mbps, each word contains a new data byte. when the port is operating at 10 mbps, each data byte is repeated 10 times. table 43. intel ? lxt9785/lxt9785e smii signal summary signal to from purpose txdata phy mac transmit data & control sync phy mac synchronization rxdata mac phy receive data & control refclk mac & phy system synchronization 1. refer to table 7, ?intel? lxt9785/lxt9785e smii specific signal descriptions ? pqfp? on page 39 for detailed signal descriptions.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 133 document number: 249241 revision number: 007 revision date: august 28, 2003 figure 15. intel ? lxt9785/lxt9785e typical smii interface diagram typical smii interface in a 16-port system 8-port media access controller ( mac) sync0 magnetics/fiber transceiver mdio0 mdc0 mdint0 8-port media access controller (mac) magnetics/fiber transceiver sync0 mdio0 mdc0 mdint0 system clk 125 mhz sourced externally or from switch asic refclk0 lxt9785/9785e 8-port phy lxt9785/9785e 8-port phy refclk1 refclk0 refclk1 8 txdata n rxdata n 8 8 8 rxdata n section section txdata n
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 134 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 figure 16. intel ? lxt9785/lxt9785e typical smii quad sectionalization diagram magnetics/fiber transceiver sync0 lxt9785/9785e 8-port phy 12-port media access controller ( mac) sync1 4 magnetics/fiber transceiver magnetics/fiber transceiver 8 sync0 8 125 mhz sourced externally or from switch asic 4 lxt9785/9785e 8-port phy 12-port media access controller ( mac) sync0 4 4 mdc0 mdc0 mdio0 mdio0 mdio0 mdc0 8 8 4-port (sec) 4-port (sec) mdio1 mdc1 refclk0 refclk1 refclk0 refclk1 refclk0 refclk1 txdata n rxdata n txdata n rxdata n txdata n rxdata n mdint1 mdint0 mdint0 mdint0 txdata n rxdata n section section section vcc lxt9785/9785e typical smii interface in a 24-port system
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 135 document number: 249241 revision number: 007 revision date: august 28, 2003 4.7.1 smii reference clock the refclk operates at 125 mhz. the transmit and receive data a nd control streams must always be synchronized to the refclk by the mac and phy. the lxt9785/lxt9785e samples these signals on the rising edge of the refclk. 4.7.2 txsync pul se (smii/ss-smii) the txsync pulse delimits segm ent boundaries and synchronizes with refclk. the mac must continuously generate a txsync pulse once every 10 refclk cycles. the txsync pulse signals the start of each new segment ( see figure 21 on page 140 ). 4.7.3 transmit data stream transmit data and control informat ion are signaled in ten- bit se gments. in 100 mbps mode, each segment contains a new byte of data. in 10 mbps mode, the mac must repeat a 10m serial word ten times on txdata. the lxt9785/lxt9785e may sample that serial word at any point. the txsync pulse signals the start of a new segment as shown in figure 18 . 4.7.3.1 transmit enable the mac must assert the txen bit in each segment of txdata, and de-assert txen n after the last segment of the packet. 4.7.3.2 transmit error when the mac asserts the txer bit in 100ba se-x mode, the lxt9785/lxt9785e drives ?h? symbols onto the network interface. txer doe s not have any functio n in 10m operation. figure 17. intel ? lxt9785/lxt9785e 100 mbps serial mii data flow 4b/5b s0 s1 s2 s3 s4 d0 d1 d2 d3 d4 d5 d6 d7 s0 s1 serial data stream strip tx_en & tx_er status bits insert crs & rx_dv status bits d0 d1 d2 d3 d0 d1 d2 d3 2 nibbles tx/rx data s0 s1 s2 s3 s4 2 symbols tx/rx data to/from mac to/from pmd sublayer
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 136 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 4.7.4 receive data stream receive data and control information are signalled in ten-bit segments. in 100 mbps mode, each segment contains a new byte of data. in 10 mbps mode, each segment is repeated ten times (except for the crs bit), and the mac can sample any of the ten segments. 4.7.4.1 carrier sense the crs bit (slot 0) is generate d when a packet is received from the network interface. the crs bit is set in real time, even in 10 mbps mode (all other bits are re peated in 10 sequential segments). 4.7.4.2 receive data valid the lxt9785/lxt9785e asserts the rx_dv bit (s lot 1) when it receives a valid packet. the assertion timing changes depe nding on line operating speed: ? for 100base-tx and 100base-fx links, the rx_dv bit is asserted from the first nibble of preamble to the last nibbl e of the data packet. ? for 10base-t links, the entire preamble is tr uncated. the rx_dv bit is asserted with the first nibble of the start-of-frame delimiter (sfd) ?5d? and remains asserted until the end of the packet. 4.7.4.3 receive error when the lxt9785/lxt9785e receives an invalid symbol from the network in 100base-tx mode, it drives ?0101? on the associated rxdata signals. 4.7.4.4 receive status encoding the lxt9785/lxt9785e encodes status information onto the rxdata line during ipg as seen in table 44 on page 137 . status bit rxdata<5> indicates the validity of the upper nibble (rxdata<7:4> of the last byte of the previous frame). rxdata and rx_dv are passed through the internal elasticity fifo to smooth any clock rate differences between the recovered clock and the 125 mhz reference clock. 4.7.5 collision the smii interface does not provi de a collision output and relie s on the mac to interpret col conditions using crs and txen. crs is unaffected by the transmit path. figure 18. intel ? lxt9785/lxt9785e serial mii transmit synchronization txd0 txd1 txd2 txd3 txd4 txd5 txd6 txd7 clock txsync tx txen txer txer
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 137 document number: 249241 revision number: 007 revision date: august 28, 2003 4.7.6 source synchronous-serial media independent interface some system designs require the phy to be placed between 3 to 12 inches away from the mac. a new source synchronous-serial me dia independent inte rface (ss-smii) definition has been added because of this requirement. to provide a so urce synchronous interface between the phy and mac, the phy must drive the rxclk and the rxs ync signals to the mac. also, the mac must drive the txclk and the txsync signal to the phy. the refclk is also needed to synchronize the data to the phy?s core clock domain. txdata is clocked in using txclk and then synchronized to refclk and transmitted to the tw isted-pair. the rxdata is synchronized to the rxclk. see figure 23 on page 141 . figure 19. intel ? lxt9785/lxt9785e serial mii receive synchronization table 44. intel ? lxt9785/lxt9785e rx status encoding bit definitions signal definition crs carrier sense - identical to mii, except that it is not an asynchronous signal. rxdv receive data valid - identical to mii. when rx_dv = 0, status information is transmitted to the mac. when rx_dv = 1, received data is transmitted to the mac. 0 = status byte 1 = valid data byte rxer (rxdata0) inter-frame status bit rxdata0 indicates whether or not the phy detected an error somewhere in the previous frame. 0 = no error 1 = error speed (rxdata1) inter-frame status bit rxdata1 indicates port operating speed. 0 = 10 mbps 1 = 100 mbps duplex (rxdata2) inter-frame status bit rxdata2 indicates port duplex condition. 0 = half-duplex 1 = full-duplex link (rxdata3) inter-frame status bit rxdat a3 indicates port link status. 0 = down 1 = up jabber (rxdata4) inter-frame status bit rxdat a4 indicates port jabber status. 0 = ok 1 = error valid (rxdata5) inter-frame status bit rxdata5 c onveys the validity of the upper nibble of the last byte of the previous frame 0 = invalid 1 = valid false carrier (rxdata6) inter-frame status bit rxdata6 indicates whether or not the phy has detected a false carrier event. 0 = no fc detected 1 = fc detected rxdata7 this bit is set to 1. 1 = always 1. both rxdata0 and rxdata5 bits are valid in the segm ent immediately following a frame, and remain valid until the first data segment of the next frame begins. cr s rx_dv rxd0 rxd1 rxd2 rxd3 rxd4 rxd5 rxd6 rxd7 crs clock rxsync rx rxer speed duplex link j abber valid fce rxd7
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 138 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 table 45. intel ? lxt9785/lxt9785e ss-smii signal to from purpose txdata phy mac transmit data & control txclk phy mac transmit clock txsync phy mac synchronization pulses rxdata mac phy receive data & control rxclk mac phy receive clock rxsync mac phy receive synchronization refclk mac system synchronization
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 139 document number: 249241 revision number: 007 revision date: august 28, 2003 figure 20. intel ? lxt9785/lxt9785e typical ss-smii interface diagram typical ss-smii interface in a 16-port system 8-port media access controller ( mac) txsync0 magnetics/fiber transceiver txclk0 rxsync1 rxclk1 mdio0 mdc0 mdint0 8-port media access controller (mac) magnetics/fiber transceiver txsync0 rxsync1 mdio0 mdc0 mdint0 sys_clk txclk0 rxclk1 refclk0,1 lxt9785/9785e 8-port phy lxt9785/9785e 8-port phy refclk0,1 125 mhz sourced externally or from switch asic rxdata n 8 8 8 8 n txdata section section txdata n rxdata n
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 140 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 figure 21. intel ? lxt9785/lxt9785e typical ss-smii quad sectionalization diagram magnetics/fiber transceiver txsync0 rxsync1 txclk0 rxclk1 lxt9785/9785e 8-port phy 12-port media access controller ( mac) txsync1 4 magnetics/fiber transceiver txdata n txclk1 rxsync1 rxclk1 rxdata n magnetics/fiber transceiver 8 txsync0 rxsync1 8 125 mhz sourced externally or from switch asic 4 txclk0 rxclk1 lxt9785/9785e 8-port phy 12-port media access controller ( mac) txsync0 4 txdata n txclk0 rxsync0 rxclk0 rxdata n 4 mdc0 mdc0 mdio0 mdio0 mdio0 mdc0 8 8 4-port (sec) 4-port (sec) mdio1 mdc1 refclk0 refclk1 refclk0 refclk1 refclk0 refclk1 mdint0 mdint0 mdint1 txdata n rxdata n rxdata n txdata n mdint0 section section section vcc typical ss-smii interface in a 24-port system lxt9785/9785e
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 141 document number: 249241 revision number: 007 revision date: august 28, 2003 4.8 rmii operation the lxt9785/lxt9785e provides an independent re duced mii port for each network port. each rmii uses four signals to pass received data to the mac: rxdata n <1:0>, rxer n , and crs_dv n (where n reflects the port number). three signals ar e used to transmit data from the mac: txdata n _<1:0> and txen n . both receive and transmit signal s are clocked by refclk. data transmission across the rmii is implemented in di-bit pairs which equal a 4-bit wide nibble. note: the bga15 package does not support the rmii interface. 4.8.1 rmii reference clock the lxt9785/lxt9785e requires a 50 mhz refe rence clock (refclk). the device samples the rmii input signals on the rising edge of refclk and drives rmii output signals on the falling edge. figure 22. intel ? lxt9785/lxt9785e ss-smii transmit timing figure 23. intel ? lxt9785/lxt9785e ss-smii receive timing txclk txsync txdata all signals are synchronous to the clock txer txen txd2 txd0 txd1 txd3 txd4 txd5 txd7 txd6 txclk txsync txdata txer dplx frcerr speed jabr link txen txer txer rxclk rxsync rxdata all signals are synchronous to the clock crs rxdv rxd2 rxd0 rxd1 rxd3 rxd4 rxd5 rxd7 rxd6 rxclk rxsync rxdata crs dplx rxer speed upnib jabr flscar link rxdv crs crs
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 142 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 4.8.2 transmit enable txen n must be asserted and de-asserted synchr onously with refclk. the mac must assert txen n at the same time as the fi rst nibble of preamble. txen n must be de-asserted after the last bit of the packet. 4.8.3 carrier sense & data valid the lxt9785/lxt9785e asserts crs_dv n when it detects activity on the line. however, rxdata n outputs zeros until the received data is decoded and available for transfer to the controller. 4.8.4 receive error whenever the lxt9785/lxt9785e receives an erro r symbol from the network, it asserts rxer n . when it detects a bad start-of-str eam delimiter (ssd) it drives a ?10? jam pattern on the rxdata pins to indicate a false carrier event. 4.8.5 out-of-band signaling the lxt9785/lxt9785e has the capability of enc oding status information in the rxdata stream during ipg. see ?monitoring operations? on page 157 for details. 4.8.6 4b/5b coding operations the 100base-x protocol specifies the use of a 5-bit symbol code on the network media. however, data is normally transmitted across the rmii in terface in 2-bit nibblets or ?di-bits?. the lxt9785/ lxt9785e incorporates a parallel/serial converter that translates between di-bit pairs and 4-bit nibbles, and a 4b/5b encoder/deco der circuit that translates be tween 4-bit nibbles and 5-bit symbols for the 100base-x connection. figure 24 shows the data conversion flow from nibbles to symbols. table 46 on page 147 shows 4b/5b symbol coding (not all symbols are valid). figure 24. intel ? lxt9785/lxt9785e rmii data flow d2 d3 d0 d1 parallel to serial serial to parallel d0 d1 d2 d3 4b/5b s0 s1 s2 s3 s4 mlt3 0 +1 -1 00 transition = 1. no transition = 0. all transitions must follow pattern: 0, +1, 0, -1, 0, +1... scramble de- scramble reduced mii mode data flow di-bit pairs 4-bit nibbles 5-bit symbols
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 143 document number: 249241 revision number: 007 revision date: august 28, 2003 figure 25. intel ? lxt9785/lxt9785e typical rmii interface diagram 50 mhz sourced externally or from switch asic magnetics/fiber transceiver typical rmii interface in a 16-port system 8-port media access controller ( mac) magnetics/fiber transceiver 8 8 lxt9785/9785e 8-port phy 8-port media access controller ( mac) mdc0 mdio0 mdio0 mdc0 8 8 8 8 8 8 8 8 refclk0 8 8 8 8 txd0 n txd1 n txen n rxd0 n rxd1 n crs_dv n rxer n lxt9785/9785e 8-port phy mdint0 mdint0 txd0 n txd1 n txen n rxd0 n rxd1 n crs_dv n rxer n refclk1 refclk0 refclk1 section section
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 144 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 figure 26. intel ? lxt9785/lxt9785e typical rmii quad sectionalization diagram magnetics/fiber transceiver 12-port media access controller ( mac) txd1 n 4 magnetics/fiber transceiver txd0 n magnetics/fiber transceiver 8 8 50 mhz sourced externally or from switch asic 4 lxt9785/9785e 8-port phy 12-port media access controller ( mac) 4 4 mdc0 mdc0 mdio0 mdio0 mdio0 mdc0 8 8 4-port (sec) 4-port (sec) mdio1 mdc1 refclk0 8 8 8 8 8 8 refclk1 4 4 4 4 4 4 4 4 4 4 refclk1 8 8 8 8 refclk0 txd0 n txd1 n txen n rxd0 n rxd1 n crs_dv n rxer n lxt9785/9785e 8-port phy mdint0 txd0 n txd1 n txen n rxd0 n rxd1 n crs_dv n rxer n mdint0 txen n rxd0 n rxd1 n rxer n mdint1 crs_dv n mdint0 txd0 n txd1 n txen n rxd0 n rxd1 n crs_dv n rxer n section section section vcc refclk1 refclk0 typical rmii interface in a 24-port system lxt9785/9785e
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 145 document number: 249241 revision number: 007 revision date: august 28, 2003 4.9 100 mbps operation 4.9.1 100base-x network operations during 100base-x operation, th e lxt9785/lxt9785e transmit s and receives 5-bit symbols across the network link. figure 27 shows the structure of a standard frame packet. when the mac is not actively transmitting data, the lxt9785/l xt9785e sends out idle symbols on the line. in 100base-tx mode, the device scrambles the data and transmits it to the network using mlt-3 line code. the mlt-3 signals received from the ne twork are de-scrambled and decoded, and sent across the rmii to the mac. in 100base-fx mode, the lxt9 785/lxt9785 e transmits and receives nrzi signals across the lvpecl interface. an external 100 base-fx transceiver module is required to complete the fiber connection. as shown in figure 27 , the mac starts each transmission with a preamble pattern. as soon as the lxt9785/lxt9785e detects the start of preamble, it transmits a j/k start-of-stream delimiter (ssd) symbol to the network. it then encodes a nd transmits the rest of the packet, including the balance of the preamble, the start-of-frame de limiter (sfd), packet data, and crc. once the packet ends, the lxt9785/lxt9785e transmits th e t/r end-of-stream delimiter (esd) symbol and then returns to transmitting idle symbols. 4.9.2 100base-x protocol sublayer operations in a 7-layer communications model, the lxt9785/ lxt9785e is a physical layer 1 (phy) device. the lxt9785/lxt9785e implements the physical coding sublayer (pcs), physical medium attachment (pma), and physical medium depe ndent (pmd) sublayers of the reference model defined by the ieee 802.3u specification. the following paragraphs discuss the lxt9785/ lxt9785e operation from the reference model point of view. 4.9.2.1 pcs sublayer the physical coding subl ayer (pcs) provides the rmii interfac e, as well as the 4b/5b encoding/ decoding function. for 100base-tx and 100base-fx operation, the pcs layer provides idle symbols to the pmd-layer line driver as long as txen is de-asserted. for 10t operation, the pcs layer merely provides a bus interface and serial ization/de-serialization function. 10t operation does not use the 4b/5b encoder. figure 27. intel ? lxt9785/lxt9785e 100base-x frame format p0 p1 p6 sfd 64-bit preamble (8 octets) start-of-frame delimiter (sfd) da da sa sa destination and source address (6 octets each) l1 l2 packet length (2 octets) d0 d1 dn data field (pad to minimum packet size) frame check field (4 octets) crc i0 interframe gap / idle code (> 12 octets) replaced by /t/r/ code-groups end-of-stream delimiter (esd) ifg replaced by /j/k/ code-groups start-of-stream delimiter (ssd)
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 146 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 4.9.2.1.1 preamble handling when the mac asserts txen, the pcs substitutes a /j/k/ symbol pair, also known as the start-of- stream delimiter (ssd), for the first two ni bbles received across the rmii. the pcs layer continues to encode the remaining rmii data until txen is de-asserted (see table 46 on page 147). it then returns to supplying idle symbols to the line driver. the pcs layer performs the oppos ite function in the receive dir ection by substituting two preamble nibbles for the ssd. figure 28. intel ? lxt9785/lxt9785e protocol sublayers encoder/decoder serializer/de-serializer link/carrier detect pcs sublayer pma sublayer mii interface lvpecl interface fiber transceiver lxt9785 100base-tx 100base-fx scrambler/ de-scrambler pmd sublayer
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 147 document number: 249241 revision number: 007 revision date: august 28, 2003 4.9.3 pma sublayer the 100base-x pma protocol uses the 4b/5b data encoding scheme to encode/decode the data streams. the coding scheme is shown in table 46 . table 46. 4b/5b coding code type 4b code 3 2 1 0 name 5b code 4 3 2 1 0 interpretation 0 0 0 0 0 1 1 1 1 0 data 0 0 0 0 1 1 0 1 0 0 1 data 1 0 0 1 0 2 1 0 1 0 0 data 2 0 0 1 1 3 1 0 1 0 1 data 3 0 1 0 0 4 0 1 0 1 0 data 4 0 1 0 1 5 0 1 0 1 1 data 5 0 1 1 0 6 0 1 1 1 0 data 6 data 0 1 1 1 7 0 1 1 1 1 data 7 1 0 0 0 8 1 0 0 1 0 data 8 1 0 0 1 9 1 0 0 1 1 data 9 1 0 1 0 a 1 0 1 1 0 data a 1 0 1 1 b 1 0 1 1 1 data b 1 1 0 0 c 1 1 0 1 0 data c 1 1 0 1 d 1 1 0 1 1 data d 1 1 1 0 e 1 1 1 0 0 data e 1 1 1 1 f 1 1 1 0 1 data f idle undefined i 1 1 1 1 11 idle. used as inter stream fill code. 0 1 0 1 j 2 1 1 0 0 0 start-of-stream delimiter (ssd), part 1 of 2. control 0 1 0 1 k 2 1 0 0 0 1 start-of-stream delimiter (ssd), part 2 of 2. undefined t 3 0 1 1 0 1 end-of-stream delimiter (esd), part 1 of 2. undefined r 3 0 0 1 1 1 end-of-stream delimiter (esd), part 2 of 2. undefined h 4 0 0 1 0 0 transmit error. used to force signaling errors. undefined invalid 0 0 0 0 0 invalid undefined invalid 0 0 0 0 1 invalid undefined invalid 0 0 0 1 0 invalid invalid undefined invalid 0 0 0 1 1 invalid undefined invalid 0 0 1 0 1 invalid undefined invalid 0 0 1 1 0 invalid undefined invalid 0 1 0 0 0 invalid undefined invalid 0 1 1 0 0 invalid undefined invalid 1 0 0 0 0 invalid undefined invalid 1 1 0 0 1 invalid 1. the /i/ (idle) code group is se nt continuously between frames. 2. the /j/ and /k/ (ssd) code groups are always sent in pairs; /k/ follows /j/. 3. the /t/ and /r/ (esd) code groups are al ways sent in pairs; /r/ follows /t/. 4. an /h/ (error) code group is used to signal an error condition.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 148 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 4.9.3.1 link in 100 mbps mode, the lxt9785/lxt9785e establishes a link whenever the descrambler becomes locked and remains lock ed for approximately 50 ms. wh enever the descrambler loses lock (<12 consecutive idle symbols during a 2 ms window), the link is taken down. this provides a robust link, filtering out any small noise hits that may otherwise disrupt the link. furthermore, 100 mbps idle patterns will not bring up a 10 mbps link. the lxt9785/lxt9785e reports link failure via the regi ster status bits (1.2, 17.10, and 19.4) and interrupt functions. if auto-negotiate is enable d, link failure causes the device to re-negotiate. 4.9.3.2 link failure override the lxt9785/lxt9785e normally transmits 100 mbps data packets or idle symbols only if it detects the link is up, and transmits only flp burs ts if the link is not up. setting bit 16.14 = 1 overrides this function, allowing the lxt9785/lxt9785e to transmit data packets even when the link is down. this feature is provided as a diagnostic tool. note: auto-negotiation must be disabled to transmit data packets in the absence of link. if auto- negotiation is enabled, the lxt9785/lxt9785e au tomatically begins transmitting flp bursts if the link goes down. 4.9.3.3 carrier sense/data valid (rmii) the lxt9785/lxt9785e asserts cr s_dv whenever the respective port receiver is in a non-idle state (as defined by the rmii sp ecification revision 1.2), includin g false carrier events. assertion of crs_dv is asynchronous with respect to refc lk. in the event that si gnal decoding is not complete when crs_dv is asserted, the lxt9785/lxt9785e outputs 00 on the rxdata1:0 lines until the decoded data are available. when the line returns to an idle state, crs_dv is de-asserted synchronously with respect to refclk. if the fifo still contains data to be passed to the mac via th e rmii when crs is de- asserted, crs_dv toggles on nibble boundaries until the fifo is empty. for 100base-x signals, crs_dv toggles at 25 mhz. for 10base-t signals, crs_dv toggles at 2.5 mhz. 4.9.3.4 carrier sense (smii) for 100base-tx and 100base-fx links, a start-of -stream delimiter (ssd) or /j/k/ symbol pair causes assertion of carrier sense (crs). an end-of -stream delimiter (esd), or /t/r/ symbol pair causes de-assertion of crs. the pma layer also de-asserts crs if idle symbols are received without /t/r/. in this event, receive error is indicat ed during the ipg until the next packet is received. for 10t links, crs assertion is based on receipt of valid preamble, and de-assertion on receipt of an end-of-frame (eof) marker. 4.9.3.5 receive data valid (smii) the lxt9785/lxt9785e asserts the rx_dv bit when it receives a valid packet. however, rxdata outputs zeros until the receive d data are decoded and available for transfer to the controller.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 149 document number: 249241 revision number: 007 revision date: august 28, 2003 4.9.3.6 twisted-pair pmd sublayer the twisted-pair physical medium dependent (p md) layer provides the signal scrambling and descrambling, line coding and decoding (mlt-3 for 100base-tx, manchester for 10t), as well as receiving, polarity co rrection, and baseline wander correction functions. 4.9.3.6.1 scrambler/descrambler (100base-tx only) the purpose of the scrambler is to spread the signal power spect rum and further reduce emi using an 11-bit, non-data-dependent polynomial. the receiver automatically decodes the polynomial whenever idle symbols are received. the scrambler/descrambler can be bypassed by sett ing register bit 16.12 = 1. the scrambler is automatically bypassed when the fiber port is enab led. scrambler bypass is provided for diagnostic and test support. 4.9.3.6.2 baseline wander correction the lxt9785/lxt9785e provides a baseline wander correction function which makes the device robust under all network operating conditions. the mlt3 coding scheme used in 100base-tx is, by definition, ?unbalanced?. this means that the dc average va lue of the signal voltage can ?wander? significantly over short time intervals (tenths of seconds). this wander may cause receiver errors, particularly in less robust design s, at long line lengths (100 meters). the exact characteristics of the wander ar e completely data dependent. the lxt9785/lxt9785e baseline wander correction characteristics allow the device to recover error-free data while receiving worst-case ?killer? packets over all cable lengths. 4.9.3.6.3 polarity correction the lxt9785/lxt9 785e automatically detects and correct s for the condition where the receive signal (tpfip/n) is inverted. reversed polarity is detected if eight inverted link pulses or four inverted end-of-frame (eof) ma rkers are received consecutively. if link pulses or data are not received by the maximum receive time- out period, the polarity state is reset to a non-inverted state. before the polarity switch occurs, every frame is inverted and cause s rxer to assert. the specific number of rxer events observed depends on how many link pulses occur between packets. 4.9.3.7 fiber pmd sublayer the lxt9785/lxt9 785e provides an lvpecl in terface for connection to an external 3.3 v or 5 v fiber-optic transceiver. (the external tran sceiver provides the pmd function for the optical medium.) the lxt9785/lx t9785e uses a 125 mbaud nrzi fo rmat for the fiber interface, and does not support 10base-fl applications. note: the bga15 package does not support fiber interface. 4.9.3.7.1 far end fault indications the lxt9785/lxt9785e signal detect pins independently detect signal faults from the local fiber transceivers via the sd pins. the device also uses register bit 1.4 to report remote fault indications received from its link partner. the device ?ors? both fault conditions to set bit 1.4. register bit 1.4 is set once and clears when read.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 150 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 the far-end fault detection process in fiber operation requires idles to establish link. link will not establish if a far-end fault pattern is the initial signal detected. either fault condition causes the lxt9785/lxt9785e to drop the link unless forced link pass is selected (16.14 = 1). link down condition is then reported via interrupts and status bits. in response to locally detected signal faults (sd activated by the local fiber transceiver), the affected port can transmit the far en d fault code if fault code transmission is enabled by register bit 16.2. ? when register bit 16.2 = 1, transmission of the far end fault code is enabled. the lxt9785/ lxt9785e transmits far end fault code if fault conditions are detected by the signal detect pins. ? when register bit 16.2 = 0, the lxt9785/lxt978 5e does not transmit far end fault code. it continues to transmit idle code and may or may not drop link depending on the setting for register bit 16.14. the occurrence of a far end fault causes all transmi ssion of data from the reconciliatio n sublayer to stop and the far end fault code to begin. the far end fault code consists of 84 ones?s followed by a single ?0? and is repeated until the far end fault condition is removed. 4.10 10 mbps operation the lxt9785/lxt9785e operates as a standard 10base-t transceiver and supports all the standard 10 mbps functions. during 10base-t (10t) operation, the lxt9785/lxt9785e transmits and receives manchester-encoded data across the network link. when the mac is not actively transmitting data, the device sends out link pulses on the line. in 10t mode, the polynomial scrambler/descrambler is inactive. manchester-encoded signals received from the network are decoded by the lx t9785/lxt9785e and sent across the mii to the mac. note: the lxt9785/lxt9785e does not support fiber connections at 10 mbps. 4.10.1 preamble handling the lxt9785/9785e offers two options for preamble handling, which are selected by register bit 16.5. in 10base-t mode, when register bit 16.5 = 0, the device strips the preamble off the received packets. in rmii and the smii modes, the crs signal is asserted based upon receive activity. in the smii modes, ou t-of-band (oob) signaling is pres ent until the sfd is output. the dv signal is initially asserted in the frame that the sfd is output . in rmii mode, zeros are output after receive activity is detected until the sfd is output. the pack et is output following the sfd. when register bit 16.5 = 1 in 10base-t mode, the lxt9785/lxt9785e passes the preamble through the rmii and the smii interfaces. in rmii a nd the smii modes, the crs signal is asserted based upon receive activity. in the smii modes, oob signaling is continued un til preamble is available from the receive fifo. af ter the preamble, the sfd is output with the initial assertion of the dv signal. the rmii interface ou tputs zeros after receive activity is detected un til preamble is available from the fifo. the number of zero nibbl es output before preamble is based upon the fifo initial fill settings (register bits 18.15 :14). the preamble is followed by the sfd and the packet body. register bit 16.5 has no effect in 100 mbps operation.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 151 document number: 249241 revision number: 007 revision date: august 28, 2003 4.10.2 dribble bits the lxt9785/lxt9785e device handles dribble bits in all modes. if one thr ough four dribble bits are received, the nibble is passed across the rmii. if five through seven dribble bits are received, the second nibble is not sent onto the rmii bus. 4.10.3 link test the lxt9785/lxt9785e always transmits link pulses in 10t mode. when enabled, the link test function monitors the connection for link pulses. once link pulses are detected, data transmission is enabled and remains enabled as long as either the li nk pulses or data transmission continue. if link pulses stop, the data transmission is disabled. if the link test function is disabled, the lxt9785 /lxt9785e transmits to the connection regardless of detected link pulses. the link test function is disabled by setting register bit 16.14 = 1. 4.10.3.1 link failure link failure occurs if link test is enabled and link pulses or packets stop being received. if this condition occurs, the lxt9785/lxt9785e return s to the auto-negotiation phase if auto- negotiation is enabled. 4.10.4 jabber if a transmission exceeds the jabber timer, th e lxt9785/lxt9785e disables the transmit and loopback functions and the collision status bit (r egister bit 17.11) is set regardless of duplex. the jabber timer, according to the ieee standard, must be between 20 ms to 150 ms. the rmii does not include a jabber pin, but the mac may read register 1 to determine jabber status. the lxt9785/lxt9785e automatically exits jabber mode after the unjab time expires. this function is disabled by setting register bit 16.10 = 1.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 152 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 4.11 dte discovery process the dte discovery process is port dependent and must be enabled through software. the process is implemented as a next page option to the auto -negotiation flow. when the process is enabled, manual control of auto-negotiation next pages is not allowed. this feature applies to the lxt9785e transceiver only. the process depends upon an ip phone, or any other dte capable of being powered remotely, having a specific filter that pass es nlps and flps. this filter should be non-polarized to insure that the latest status of auto-m dix operation does not effect op eration. this filter attenuates 100 mbps mlt3 signals and 10 mbps manchester-e ncoded signals, and must be bypassed when power is applied to the ip phone. figure 29 shows a typical ip telephone system connection. 4.11.1 definitions the following terms are used throughout the dte discovery sections: figure 29. typical ip telephone system connection power outlet computer 123 456 789 * 8# ip telephone ups/ generator power cable sd power fault 123 456 789101112 link mode mode link 13 14 1 5 16 17 18 19 2 1 20 2 2 23 24 mode select fdx act 1x 2x 3x 4x 5x 6x 7x 8x 9x 10x 11x 12x 13x 14x 15x 16x 17x 18x 19x 20x 21x 22x 23x 24x 10/100base -t ports 100 reset clear module status se lf te st console pr ocurve switch 2 424m hp j4122b voip-enabled switch power outlet data only over category 5 cable power cable power and data over category 5 cable negotiation process: this includes auto-negotiation and parallel detection processes system: the switch system using the lxt9785e for dte discovery link partner: a device connected to the lxt9785e through twisted pair cables dte: data terminal equipment; any end-of-link partner standard link partner: a link partner that is not requiring power over a category 5 cable; typically a pc remote-power dte: data terminal equipment requiring power over a category 5 cable; typically an ip telephone discovery: the process of identifying the type of link partner present
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 153 document number: 249241 revision number: 007 revision date: august 28, 2003 4.11.2 interaction between processor, mac, and phy the state machines that contro l the mechanics of the discover y process reside within the lxt9785e device. however, control of the power su pply and overall system control reside in the system processor. the processor communicates with the power supply unit (psu) and switches it on and off dependant on the data that is supplied by the phy. the phy register data is read by the mac using the mdio interface. the required control bits are contained in the phy device register map and are discussed in detail in the section labeled ?management interface and control? on page 153 . note: the details of the processor/mac interface and the processor/psu interf ace are implementation specific and therefore are out of the scope of this specification. the following is an overview of the system co ntrol for a successful remo te-power dte discovery: 1. the discovery process is enabled by the dte di scovery process enable (dis_en) register bit 27.6 and the auto-negotiation enable register bit 0.12. writing register bit 27.6 immediately affects the auto-negotiation ba se page. if already enabled, auto-negotiation should be restarted after this bit is written to ensure proper operation. register bit 4.15 is used for manual control of auto-negotiation next pages and should be left in the default state (cleared). 2. the lxt9785e phy then tests to see if a remote -power dte is present as the link partner. if a remote-power dte is found, the power enable (power_en) register bit 27.4 is set. the processor polls this signal via the mac. 3. upon detecting a remote-power dte, the processor instructs the power supply to switch on. once power has been applied to the dte, normal negotiation takes place. the processor must enable the required negotiation process by restarting auto-negotiation, or by setting forced speed mode after power has been applied. the pr ocessor must poll the link-up register bit 1.2 for the corresponding lxt9785e port, or the link status change interrupt, to ensure that the link has been established. 4. a time-out must be connected wi th this feature so that if link is not established within a pre- determined time period (system dependant), the processor instructs the power supply to switch off. if link is not established prior to the expiration of the ?link fail inhibit timer?, the lxt9785e restarts negotiation with dte detec tion if auto-negotiation mode was used to establish link with the phone, and the dte process is still enabled. the lxt9785e restarts negotiation without dte detection if either forced speed mode is used to establish link with the phone, or the dte process is disabled. 5. if power is applied and link is established, the system must still poll the link status register bit 1.2 for the corresponding lxt9785e port or the link status change interrupt. this is required since link status is the only way to know when the remote-power dte is removed or unplugged. on seeing the link_down condition, the processor instructs the power supply to switch off, and the dte discovery begins again or is disabled. 4.11.3 management interface and control the management and control of the dte discovery process is via the mdio port. each port on the lxt9785e is capable of running the discovery process, thus each port is independ ently controlled. this is achieved by each port having a dedicated set of control and status bits. these bits are found in register 27 as follows:
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 154 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 dte discovery process enable - register bit 27.6 (dis_en) r/w default value = 0: disabled. register bit 27.6 controls the operation of the pr ocess. the discovery process is disabled when register bit 27.6 = 0, and enabled when register b it 27.6 = 1. the mac controller sets register bit 27.6 to a 1 when a port search for a dte requiring power is desired. once set, register bit 27.6 remains = 1 until the mac clears it, either by directly clearing it or by resetting the phy. this allows the discovery process to continue to function if unsuccessful in detecting a dte, without being continually re-enabled by the mac. if regist er bit 27.6 is set after link is established, no action is taken until after the link goes down. power enable - register bit 27.4 (power_en) r default value = 0: no remote-power dte found. register bit 27.4 contains the result of the disc overy process. when register bit 27.4 = 0, the discovery process has not found remote-power dte, and when register bit 27.4 = 1, the discovery process has potentially found a dte requiring power. this indicates power should be applied to the category 5 cable. register bit 27.4 is polled by the mac during the discovery process, and is cleared when the phy is reset, wh en auto-negotiation is restarted, or when auto- negotiation is disabled. in the ev ent of a discovery process being interrupted due to detection of an already powered link partner (auto-negotiation co mpletion or parallel detection), register bit 27.4 = 0. standard link partner detected - register bit 27.3 (slp_det) r/w clear on read default value = 0: no link partner found. when register bit 27.3 = 1, a standard link partner has been detected by the lxt9785e (nlps, mlt3 data, flps without next page support, or flps with non-matching next pages). this indicates power should not be applied to the category 5 cable. when register bit 27.3 = 0, other bits are checked to determine overal l status of the link partner. register bit 27.3 is cleared on read, or dte discovery is disabled, link is established, or auto-negotiation is either restarted or disabled. link fail timeout - register bit 27.2 (lfit expired) r/w clear on read default value = 0 (link fail inhibit timer has expired without establishment of link with a standard link partner). valid only when standard link partner detected register bit 27.3 = 1. register bit 27.2 is set if link is not established prior to the link fail inhibit timer expiring. this indicates that the discovery process has restarted and the standard link partner detected register bit may no longer be valid. register bit 27.2 is cleared on read, or dte di scovery is disabled, link is established, or auto-negotiation is either restarted or disabled. 4.11.4 dte discovery process flow the following section describes the dte discovery process.see figure 30, ?intel? lxt9785e negotiation flow chart? on page 156 for a flow chart of the discovery process.when dte discovery (27.6) and auto-negotiation (0.12) are en abled (auto-negotiation mode is required), the lxt9785e transmits the auto-negotiation base page with the next page ability bit set ( ?auto- negotiation advertisement regi ster (address 4)? on page 204 ). system software polls register 27 to determine if or when a remote-power dte is detected. the receiver monitors the line to dete rmine if nlps, mlt3 data, or fl p bursts are being received. if the receive activity is flp bursts, the status of the next page ab ility bit is checked . if the detected ?link partner? also supports next page, then the lxt9785e transmits out the next page sequence
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 155 document number: 249241 revision number: 007 revision date: august 28, 2003 associated with message code #5 (organizationally unique identifier (oui) tag code). the definition for the next pages to be sent out for this message code include some user-defined code values. these values are loaded wi th randomly created data from an internal lsfr that is free running and seeded with the phy address of the lxt9785e port. the next pages are hard coded in the logic (the lxt9785e ignores any data wr itten into register 7) and are outlined in table 47 . the receiver monitors the next pa ges to determine that the exact next page data (especially the random data) transmitted is receive d. as soon as the fi rst non-matching next pa ge is detected, the dte discovery process is stopped and the base pa ge is used to determine the capability options. the power-enable register bit 27.4 is set when a remote-power dte is detected as the link partner, and the last next page is repeatedly transmitted until software restarts the required negotiation process (auto-negotia tion or forced-speed mode). the software should be written so that the negotiation is not restarted until the dte has been powered up over the category 5 cable. the power- enable register bit 27 .4 is cleared upon restarting or disabling auto-negotiation (selecting fo rced mode). the system must be able to detect over-current conditions and be capable of disabling power in case the link partner is not a remote- power dte. some examples of devices that would mistakenly set power-enable register bit 27.4 are a token-ring balun and a loopback cable. once link partner power has been stabilized and sufficient time has passed for the link partner to initialize, the auto-negot iation process may be restarted. the negotiation process establishes link if a compatible mode exists between the lxt9785e and the link partner. if a compatible mode does not ex ist (not compatible or not established within the link fail inhibit timer period), the lxt9785e e ither restarts auto-negotiation/dte discovery (discovery is enabled (27.6=1) and auto-negotiation is enabled (0.12 = 1)), or normal negotiation (discovery is disabled (27.6=0) and auto-negotiati on is enabled (0.12 = 1)), or either 10 mbps or 100 mbps forced-mode operation (auto-negotiation is disabled (0.12 = 0)). the software must detect this non-link state and disable power. 4.11.5 dte discovery behavior the device behavior checks the co mparison bit after each next page is successfully auto- negotiated. if the first next page or any subseque nt next page does not match, the dte discovery process transmits one last null page with the next page bit cleared to stop the dte discovery table 47. next page message #5 code word definitions next page encoding d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 oui tagged message 1a10 t 00000000101 user page 1 1 a 0 0 t 3.10 3.11 3.12 3.13 3.14 3.15 2.0 2.1 2.2 2.3 2.4 user page 2 1 a 0 0 t 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 user page 3 1 a 0 0 t 0 0 l.8 l.7 l.6 l.5 l.4 l.3 l.2 l.1 l.0 user page 4 1 a 0 0 t l.10 l.9 l.8 l.7 l.6 l.5 l.4 l.3 l.2 l.1 l.0 1. a is the acknowledge bit; t is the toggle bit; l is the lfsr
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 156 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 process. if each page is successfully auto-ne gotiated (it matches the transmitted page), dte discovery completes as previously described. the five next pages consist of a message page and four user pages. figure 30. intel ? lxt9785e negotiation flow chart default mode transmit based upon hardware configuration flp, nlp or idle symbols power up or link down 1.2 = 0 and dis_en 27.6 = 0 or link down 1.2 = 0 and forced mode software intervention auto-negotiation 0.12 = 1 (if needed) power_en 27.6 = 1 discovery base transmit flps base page (register 4) with next page 4.15 = 1 flp detected next page set? no auto negotiation determine compatibility options flp detected lfit expired 27.2 = 1 dis_en 27.6 = 1 lfit expired 27.2 = 1 dis_en 27.6 = 0 nlps or idle symbols detected yes next page transmission use random data for user defined bits as code next pages received pages = code transmitted? no parallel detection determine compatibility on speed and duplex check advertisement nlps or idle symbols detected yes dte discovered transmit last page continuously power_en 27.4 = 1 software intervention software polled power_en 27.4 = 1 turn on power supply link up compatibility lfit expired 27.2 = 1 dis_en 27.6 = 1 compatibility power on wait state for proper power assertiion set mode restart auto-negotiation or force speed auto- negotiation? yes no assumptions: auto-negotiation/forced speed set by pins advertisement requirements set by pins lfit expired 27.2 = 1 link fail timeout = 1 dis_en not set 27.6 = 0 start link down 1.2 = 0 and dis_en 27.6 = 1 and auto-neg 0.12 = 1 power applied nonmatching dte discovery np received
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 157 document number: 249241 revision number: 007 revision date: august 28, 2003 4.12 monitoring operations 4.12.1 monitoring au to-negotiation auto-negotiation may be monitored as follows: ? bits 1.2 and 17.10 = 1 once the link is established. ? additional bits in register 1 (refer to table 84, ?status register (address 1)? on page 201 ) and register 17 (refer to table 93, ?quick status register (address 17, hex 11)? on page 209 ) can be used to determine the link operating conditions and status. 4.12.2 per-port led driver functions the lxt9785/lxt9785e incorporates three direct drive leds per port (led n _1 , led n _2 , and led n _3 ). note: the bga15 package only supports two leds per port (led n _1 and led n _2). on power up, all the leds lights up for approxim ately one second after reset de-asserts. each led may be programmed to one of several differen t display modes using the led configuration register. each per-port led ma y be programmed (refer to table 96, ?led configuration register (address 20, hex 14)? on page 213 ) to indicate one of the following conditions: ? operating speed ? transmit activity ? receive activity ? collision condition ? link status ? duplex mode ? isolate condition the leds can also be programmed to display vari ous combined status co nditions. for example, setting bits 20.15:12 = 1101 produces the following combination of link and activity indications: ? if link is down, led is off. ? if link is up, led is on. ? if link is up and activity is detected, the led blinks at the stretch interval selected by bits 20.3:2 and continues to blink as long as activity is present. the led driver pins are open drain circui ts (10ma max current rating). refer to ?led circuit? on page 167 under the application information section for led circuit design details. the led configuration register also provides optional led pul se stretching to 30, 60, or 100 ms. if during this pulse stretch period, the event occurs again, the pulse stretch time is further extended (see table 96, ?led configuration register (address 20, hex 14)? on page 213 ). when an event such as receiving a packet occurs, it is edge det ected and starts the stretch timer. the led driver remains asserted until the stretch ti mer expires. if another event occurs before the stretch timer expires, the stretch timer is reset and the stretch time extended.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 158 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 when a long event (such as duplex status) occurs, it is edge detected and starts the stretch timer. when the stretch timer expires, th e edge detector is reset so that a long event causes another pulse to be generated from the edge detector. the edge detector resets the stretch timer, causing the led driver to remain asserted. figure 31 on page 158 shows how the stretch operation functions. 4.12.3 out-of-band signaling the lxt9785/lxt9785e provides an out-of-band signaling option to transfer status information across the rmii receive interface. th is feature is enabled when regi ster bit 25.0 = 1 and uses the rxdata(1:0) data bus during the inter-packet gap (ipg) time as shown in figure 32 . out-of-band signaling is disabled when isolate mode is enabled by setting register 0.10. note: the bga15 package does not support out-of-band signali ng nor the rmii interface. the two status bits transferred across the rxdata bus are software selectable via register 25 (see table 98, ?rmii out-of-band signaling re gister (address 25, hex 19)? on page 215 ). in normal operation, the lxt9785/lxt9785e stuffs the rxdata bus with zeros during the ipg. a software-selectable bit enables the rmii out-of-b and signaling feature. once this bit is set, the lxt9785/lxt9785e replaces the zeros with selected status bits during the ipg. figure 31. intel ? lxt9785/lxt9785e led pulse stretching event led note: the direct drive led outputs in this diagram are shown as active low. stretch stretch stretch figure 32. intel ? lxt9785/lxt9785e rmii programmable out-of-band signaling re fclk crs_dv rx d(1) rx d(0) data data data data data data data data st a tu s 0 st atu s 0 status 0status 0status 0status 0 st a tu s 1 st atu s 1 status 1status 1status 1status 1 0s st atu s 1 status 0 0s 1. when network activity is detec ted, the lxt9785/lxt9785e asserts cr s_dv asynchronously with respect to refclk. 2. after crs_dv is asserted, the lxt9785/lxt9785e zero-stuffs the rxdata bits until the received data has been processed through the fifo. 3. when network activity ceases , the lxt9785/lxt9785e de-asserts crs_dv synchronously with respect to refclk. crs_dv toggles until all data in the fifo has been processed through the rmii. once the fifo is empty, lxt9785/lxt9785e drives the status bits selected by the out-of-band signaling register (refer to table 98, ?rmii out-of-band signaling r egister (address 25, hex 19)? on page 215 ) on the
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 159 document number: 249241 revision number: 007 revision date: august 28, 2003 the lxt9785/lxt9785e includes an ieee 1149.1 boundary scan test port for board level testing. all digital input, output, and input/output pins are accessible. 4.12.4 boundary scan interface this interface consists of five pi ns (tms, tdi, tdo, tck and trst ). it includes a state machine, data register array, and instruction register. the tms and tdi pins are internally pulled up and the tck pin is internally pulled down. tdo does not have an internal pull-up or pull-down. 4.12.5 state machine the tap controller is a 16-state machine driven by the tck and tms pins. upon reset, the test_logic_reset state is entered. the state machine is also reset when tms and tdi are high for five tck periods. 4.12.6 instruction register the idcode instruction is always invoked after the state machine resets. the decode logic ensures the correct data flow to the data regi sters according to the curr ent instruction. valid instructions are listed in table 49 . 4.12.7 boundary scan register each boundary scan register (bsr) cell has two stages. a flip-flop and a latch are used for the serial shift stage and the parallel output stage. there are four modes of operation as listed in table 48 . refer to the identification information s ection in the lxt9785/lxt9785e specification update (document number 249357) for the jtag id numbers. table 48. bsr mode of operation mode description 1 capture 2shift 3 update 4 system function table 49. supported jtag instructions name code description data register extest 0000 hex external test bsr idcode fffe hex id code inspection id reg sample fff8 hex sample boundary bsr high z ffcf hex force float bypass clamp ffef hex clamp bsr bypass ffff hex bypass scan bypass
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 160 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 4.13 cable diagnostics overview debugging cable problems increases the overall cost of owning an d operating a local area network. cable diagnostic tools were incorporated into the lxt9785 device to help customers debug network cable problems. the cable diagnostic tool s provide the ability to detect severe cable problems, such as open and short circuits, an d determine the distance to the discontinuity. 4.13.1 features the following are three cases to consider for cable diagnostics: ? distance to a short circuit between wires of a single twisted-pair ? an open circuit ? detection of an improperly termin ated cable by the link partner. an improperly terminated cable will not meet ieee 802.3 return loss requirements. register 29 has been added to control cable testing and report cable testing results. cable diagnostics provides a method to determine the distance to opens and shorts when the link partner is inactive on the twisted-pair under test . the cable tests produce undefined results if the link partner is transmitting signals. implementation methods may vary depending upon the system use requirements of cable diagnostics. 4.13.2 operation cable diagnostics utilizes the ph y transmit drivers and receivers to test a single twisted-pair. a transmit pulse is driven down the twisted-pair under test and the reflected signal is analyzed. link partners transmitting nlp, flp, mlt3, or other tdr pulses may interfere with the ability of the lxt9785 to properly analyze the reflected cable diagnostic pulse. implementation algorithms must take these potential situations into consideration. 4.13.2.1 short and long cable testing requirements implementing cable diagnostic tests, by enabling short and long cable tests sequentially, allows more accurate measurements to a detected fault. bo th tests are necessary to reach full precision. the short and long cable tests can be run by writing 0x7400h and 0x6c00h to register 29, respectively. see section 4.13.4, ?basic implementation? on page 161 for implementation details. 4.13.2.2 precision cable diagnostics estimates the distance to a fault up to 150 m. category 5 or better cable produces the most accurate test results. less than category 5 cable may produce less accurate results on long cable lengths. cable diagnostics returns the distan ce to the closest fault, if a fault is present. cable diagnostic tests report the distance to a cable fault based on the velocity of signal propagation, which is used to determine the electri cal length to the fault. the electrical length may vary slightly from the physical cable length. the measurement accur acy may vary by +/- 2 m. the following basic equation is used to calculate the distance to a fault: distance_to_fault = (reg29[7:0] - 3.5) / 1.16
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 161 document number: 249241 revision number: 007 revision date: august 28, 2003 4.13.3 implementation considerations before performing cable diagnostics, the twisted-pair to be tested may be verified to be inactive. all applicable link configurations should be attempted. cable diagnostic tests may be started if the attempts indicate no link partners are active. if link partners are detect ed, additional tests and decisions as to next steps may need to be implem ented in the cable testing algorithm to ensure the most accurate results. intel recommends that a 100base-tx link be attempted with mdi and mdix enabled sequentially, prior to performing cable diagnostic testing, to determine if a 100base-tx-only link partner is present. if a link partner is in forced 100base-tx operation, transmitting mlt3, the cable diagnostic test result will be undefined due to the interference mlt3 causes in attempting to process the reflected cable diagnostic pulse. auto mdi/mdix on the link partner should be accounted for in derivi ng the cable te sting algorithm. intel recommends auto mdi/mdix be disabled when running the cable tests. the transmit and receive twisted-pairs must be tested one at a tim e with both short and long cable test suites. the mdi/mdix control bits in table 99, ?trim enable register (address 27, hex 1b)? on page 216 can be used to select the twisted-pair to be test ed. this requirement creates a minimum of four test permutations that must be completed to determine if the fault exists, the distance to the fault. if cable diagnostics testing is completed using a powered down lxt9785 device as the link partner, specific results can be expected. the re sults will indicate an op en connection when the pwrdwn hardware configuration pin is used. these power-down methods disable the internal termination resistors to creat e a high impedance connection eq uivalent to an open circuit. if transmit disable (register bit 16.13) or software controlled power-down (register bit 0.11) is used, the powered down device transmit logic will lo ok like an open circuit and the receive circuit will look like a 100 ? terminated connection. the transmit disable bit and the software power- down bit disable the transm it circuit but do not af fect the receive circuit. the result of cable diagnostic tests using an ip phone indicate an op en or a short fault at a gross approximation of the distance to the ip phone. th e termination resistors are not powered and do not create a proper termination. th e filter circuit used by some ma nufacturers adversely affects the test results. transmission and reception of packet s is disabled when cable diag nostics is enabled. internal loopback must be disabled for cable diagnostics to operate properly. internal loopback disables the analog interface. 4.13.4 basic implementation register 29 is used to control and report the cable diagnostics test results. the function tests one pair of the twisted-pair cable at a time. the basic process flow is described as follows (see table 100, ?cable diagnostics register (address 29, hex 1d)? on page 217 for register 29 bit definitions): 1. disable auto-negotiation by clearing register bit 0.12, set to mdi by clearing register bits 27.9:8, and ensure internal loopback is disabled, register bit 0.14 = 0. 2. write 0x7400h to register 29. setting these bits places the device in short cable cable diagnostics mode and forces link to drop. the device waits a specific amount of time (1.2 s to 1.5 s) to ensure link drops on any connected li nk partner, and initiates the cable diagnostics test on the selected twisted-pair.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 162 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 3. poll register bit 29.9. when this bit is set, the test is complete and register bits 29.7:0 contain a value used to determine if a cable fault was found and the distance to that fault. a value of 0xffh indicates no fault was found. any other va lue indicates a fault was found, that value should be stored for later use. 4. write 0x6c00h to register 29. setting these bits places the device in long cable cable diagnostics mode. 5. poll register bit 29.9. when se t, record the value of register bits 29.7:0 if a fault is found. 6. if a fault is present, a calculation is used to determine the distance to the fault. insert the smallest value recorded from register bits 29.7:0 in steps 3 and 5 above into the following formula: distance_to_fault = (reg29[7:0] - 3.5) / 1.16 register bit 29.8 is set if the fault is detected as a short circuit and is cleared if the fault is detected as an open circuit. register bits 29.12: 11 are cleared when read and are cleared during the same read cycle when regi ster bit 29.9 is read, indicating a fault condition exists. 7. normal phy operation can be resumed by writing 0x4000h to register 29 or by software or hardware reset. the test suite can be r un again by resuming at step 2 above. 4.14 link hold-off overview the phy link is established as soon as the system platform powers-up. in many cases, the system platform is not capable of supporting network operation until configuration firmware is loaded. it is desirable in such cases to prevent the phy from establishing a link until the system platform is fully configured and ready for network operation. link hold-off was incorporated into the lxt9785 device to satisfy these requirements. enabling link ho ld-off disables the phy link capability until the system platform is fully capable of supporting network operation. the feature is enabled by hardware control at power-up or software control during normal operation. 4.14.1 features link hold-off prevents the lxt9785 from establishing a link by disabling the analog transmit and receive capability. the digital capabilities of the phy are unaffected including register access and led operation. link hold-off can be enabled by an external hardware pin for all ports or by software register access for individual ports. when link hold-off is enabled, the transmitter and receiver on the selected ports are for ced into software power-down mode (see section 4.5.3, ?power-down mode? on page 127 ) to block signal activity from establishing a link and passing packets through the phy. the hardware enabled link hold-off is cont rolled by the linkhold pin. internal pull-down resistors hold the pin in the inactive state. connec ting a 5k pull-up resistor to the pin enables the feature at power-up reset or exte rnal hardware pin reset. once a phy port is programmed as desired, clearing register bit 0.11 will re-enable that port. each port must be individually re- enabled. when a port is software reset, by setting register 0.15, the state of the hardware configuration pin captured by the last hardware or power-up reset determines the default register values for the specific function for that port. link hold-off, once enabled by hardware configuration, is re- enabled on a port by issuing a software reset for that port. it is not necessary to reset the entire phy or switch system to re-enable link hold-off.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 163 document number: 249241 revision number: 007 revision date: august 28, 2003 link hold-off software control is enabled or disabled on individual ports by respectively setting or clearing register bit 0.11, the power-down bit, duri ng normal operation. it is not required to have previously enabled link hold-off by hardware configuration. link hold-off is disabled if the external pin md dis is active. the mddis pin disables the mdio interface required to re-enable no rmal transmit and recei ve link operation. m ddis is intended to disable the mdio management inte rface for unmanaged appl ications. internal loopback circuitry is unaffected in link hold-off mode. 4.14.2 operation link hold-off is implemented in one of the following two ways: ? using a hardware pin at power-up or hardware reset ? using software control through the mii management (mdc/mdio) interface. link hold-off use by an external hardware pin is as follows: 1. pull the linkhold pin high with a pull-up resistor (approximately 5 k ohms). 2. power up the system or drive the reset pin active. 3. all ports are link disabled. 4. program all ports to the desired configuration. 5. clear register bit 0.11, power -down for each individual port. 6. normal operation resumes on each port after register bit 0.11 is cleared (see table 83 for the recovery time). link hold-off is enabled on a per port basis by software control using the following two methods: method one: this method requires that link hold-off is enabled by the linkhold pin during the last power- up or hardware reset. 1. set register bit 0.15 to reset and re-enable link hold-off for the desired port. 2. program the phy to th e desired configuration. 3. clear register bit 0.11 (power-down) to disable link hold-off. 4. normal operation resumes. method two: this method enables link hold-off regardless of the linkhold hardware configuration state. 1. set register bit 0.11(power-down) to enable link hold-off for the desired port. 2. program the phy to th e desired configuration. 3. clear register bit 0.11 (power-down) to disable link hold-off. 4. normal operation resumes. note: high is defined by the io voltage supply level selected (2.5v or 3.3v).
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 164 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 5.0 application information 5.1 design recommendations the lxt9785/lxt9785e is designed to comply with ieee 802.3 requirements to provide outstanding receive bit error rate (ber), and lo ng-line-length performance. to achieve maximum performance from the lxt9785/lxt9785e, attent ion to detail and good design practices are required. refer to the lxt9785 design and layout guide application note for detailed design and layout information . 5.2 general design guidelines adherence to generally accepted design practices is essential to minimize noise levels on power and ground planes. up to 50 mv maximum of noise is considered accep table. high-frequency switching noise can be reduced, and its effects el iminated, by following th ese simple guidelines throughout the design: ? fill in unused areas of the signal planes with solid copper and attach them with vias to a vcc or ground plane that is not located adjacent to the signal layer. ? use ample bulk and decoupling capacitors throughout the design (a value of 0.01 f is recommended for decoupling caps). ? provide ample power and ground planes. ? provide termination on all high-speed switching signals and clock lines. ? provide impedance matching on l ong traces to prevent reflections. ? route high-speed signals next to a continuous, unbroken ground plane. ? filter and shield dc-dc co nverters, oscillators, etc. ? do not route any digital signals between the lxt9785/lxt9785e and the rj-45 connectors at the edge of the board. ? do not extend any circuit power and ground plane past the center of the magnetics or to the edge of the board. use this area fo r chassis ground, or leave it void. 5.2.1 power supply filtering power supply ripple and digital switching noise on the vcc plane may cause emi problems and degrade line performance. the best approach to this problem is to minimize ground noise as much as possible using good general techniques and by filt ering the vcc plane. it is generally difficult to predict in advance the performance of any design, although certain factors greatly increase the risk of having problems: ? poorly-regulated or over-burdened power supplies. ? wide data busses (32-bits+) running at a high clock rate. ? dc-to-dc converters.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 165 document number: 249241 revision number: 007 revision date: august 28, 2003 intel recommends filtering the power supply to the analog vcc pins of the lxt9785/lxt9785e. this has two benefits. first, it keeps digital switc hing noise out of the analog circuitry inside the lxt9785/lxt9785e, helping with li ne performance. second, if the vcc planes are laid out correctly, digital switching noise is kept away fr om external connectors, reducing emi problems. the recommended implementation is to break the vcc plane into two sections. the digital section supplies power to the vccd and vccio pins of the lxt9785/lxt9785e. the analog section supplies power to the vcca pins. the break between the two planes should run underneath the device. in designs with more than one the lxt9785/lxt9785e, a single continuous analog vcc plane can be used to supply them all. the digital and analog vcc planes should be joined at one or more points by ferrite beads. the beads should produce at least a 100 ? impedance at 100 mhz. beads should be placed so that current flow is evenly distributed. the maximum current rating of the beads should be at least 150% of the current that is actually expected to flow through them. a bulk cap (2.2 -10 f) should be placed on each side of each bead. in addition, a high-frequency bypass cap (0.01 f) should be placed near each analog vcc pin. 5.2.2 power and ground plan e layout considerations great care needs to be taken when laying out the power and ground planes. ? follow the guidelines in the lxt9785 design and layout guide (formerly application note 151) for locating the split between th e digital and analog vcc planes. ? keep the digital vcc plane away from the tpfo p/n and tpfip/n signals, the magnetics, and the rj-45 connectors. ? place the layers so that the tpfop/n and tfpip/n signals can be routed near or next to the ground plane. for emi reasons, it is more important to shield tpfop/n than tpfip/n. 5.2.2.1 chassis ground for esd reasons, it is a good design practice to cr eate a separate chassis ground that encircles the board and is isolated via moat s and keep-out areas from all circuit-ground pl anes and active signals. chassis ground should extend from the rj-45 connectors to the magnetics, and can be used to terminate unused signal pairs (bob smith termin ation). in single-point grounding applications, provide a single connection between chassis and circuit grounds with a 2 kv isolation capacitor. in multi-point grounding schemes (chassis and circuit grounds joined at multiple points), provide 2 kv isolation to the bob smith termination. 5.2.3 mii terminations series termination resistors are required on all th e ss-smii output signals driven by the lxt9785/ lxt9785e. special trace lay out consideration should be used wh en using the smii interface. keep all traces orthogonal and as short as possible. wh enever possible, route the clock and sync traces evenly between the longest and shortest data r outes. this minimizes r ound-trip, clock-to-data delays and allows a larger margin to the setup and hold requirements. 5.2.4 twisted-pair interface use the following standard guideli nes for a twisted-pair interface:
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 166 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 ? place the magnetics as close as po ssible to the lxt9785/lxt9785e. ? keep transmit pair traces as short as possible; both traces should have the same length. ? avoid vias and layer changes as much as possible. ? keep the transmit and receive pa irs apart to avoid cross-talk. ? route the transmit pair adjacen t to a ground plane. the optimum arrangement is to place the transmit traces two to three la yers from the ground plane, with no intervening signals. ? improve emi performance by filtering the tpo center tap. a single ferrite bead rated at 400 ma may be used to supply center tap current to all ports. 5.2.4.1 magnetic requirements the lxt9785/lxt9785e requires a 1:1 ratio for both the receive transformers and the transmit transformers. the transmit isolation voltage should be rated at 1.5 kv to protect the circuitry from static voltages across the conn ectors and cables. the lxt9785/ lxt9785e is a current driven transceiver that requires an extern al voltage (center tap) to drive the transmit signal. in order to support the auto-mdix functionality of the lxt9785/lxt9785e, the magnetic must provide a center tap for both the transmit a nd receive magnetic winding, wi th both connected to vcct. see the lxt9785/lxt9785e design and layout guide (249509-001) for magnetic testing with the lxt9785/lxt9785e. before committing to a specific component, designers should contact the manufacturer for current product specifications, and validate the magnetics for the specific application. table 50 provides the magnetics requirements. 5.2.5 the fiber interface the fiber interface consists of an lvpecl transmit and receive pa ir to an external fiber-optic transceiver. both 3.3 v fiber-optic transceivers an d 5 v fiber-optic transceivers can be used with the lxt9785/lxt9785e. see the 100base-fx fiber optic transceivers-connecting a pecl/ lvpecl interface application note (document nu mber 250781) for detailed information on fiber interface designs and recomm endations for intel phys. the following should occur in 3.3 v fibe r transceiver applications as shown in figure 36 : ? the transmit pair should be ac-coupled with 2.5 v supplies and re-biased to 3.3 v lvpecl levels table 50. intel ? lxt9785/lxt9785e magnetics requirements parameter min nom max units test condition rx turns ratio ? 1:1 ? ? tx turns ratio ? 1:1 ? ? insertion loss 0.0 0.6 1.1 db primary inductance 350 ? ? h transformer isolation ? 2 ? kv differential to common mode rejection 40 ? ? db .1 to 60 mhz 35 ? ? db 60 to 100 mhz return loss -16 ? ? db 30 mhz -10 ? ? db 80 mhz
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 167 document number: 249241 revision number: 007 revision date: august 28, 2003 ? the transmit pair should contain a balance offset in the pull-up resistors to prevent phy-to- fiber transceiver crosstalk amp lification in power-down, loopbac k, and reset states (see fiber interface application note) ? the receive pair should be dc-cou pled with an emitter current path for the fiber transceiver ? the signal detect pin should be dc-coupled with an emitter current path for the fiber transceiver refer to the fiber transceiver manufacturer?s recommendations for termination circuitry. figure 36 shows a typical example of an lxt9785/lxt 9785e-to-3.3 v fiber transceiver interface. the following occurs in 5 v fiber transceiver applications as shown in figure 37 : ? the transmit pair should be ac-coupled and re-biased to 5 v pecl input levels ? the transmit pair should contain a balance offset in the pull-up resistors to prevent phy-to- fiber transceiver crosstalk amp lification in power-down, loopbac k, and reset states (see fiber interface application note) ? the receive pair should be ac-cou pled with an emitter current path for the fiber transceiver and re-biased to 1.2 v ? the signal detect pin on a 5 v fiber transcei ver interface should use the logic translator circuitry as shown in figure 38 . refer to the fiber transceiver manufacturer?s recommendations for termination circuitry. figure 37 shows a typical example of an lxt9785/lxt9785e -to-5 v fiber transceiver interface, while figure 38 shows the interface circuitr y for the logic translator. 5.2.6 led circuit each direct drive led has a co rresponding open-drain pin. th e leds are connected through a current-limiting resistor to a positive-voltage rail. the leds are turned on when the output pin drives low. the open-drain led pins are 5 v tolerant , allowing use of either a 3.3 v or 5 v rail (a 2.5 v rail is unlikely to work with standard forward voltage leds). a 5 v rail eases led component selection by allowing more common, high-forward voltage leds to be used. refer to figure 33 for a circuit illustration. figure 33. led circuit r v led inside ic outside ic led n _m vccio < v led < 5 v + 5%
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 168 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 5.3 typical application circuits figure 34 through figure 37 on page 171 show typical application circuits for the lxt9785/ lxt9785e. figure 38 on page 172 shows the interface circuitr y for the logic translator. figure 34. intel ? lxt9785/lxt9785e power and ground supply connections gndr/gndt vccr/vcct 0.01 f gndd vccd 0.01 f + ferrite bead 10 f lxt9785/9785e 10 f digital supply plane analog supply plane vccio +2.5 v + 2.5 v or +3.3 v 0.01 f sgnd +2. 5 v or +3.3 v vccpecl gndpecl 0.1 f
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 169 document number: 249241 revision number: 007 revision date: august 28, 2003 figure 35. intel ? lxt9785/lxt9785e typical twisted-pair interface tpfop tpfon rj-45 * = 0.001 f / 2.0 kv to twisted-pair network 3 6 1 2 1:1 lxt9785/9785e 50 ? 50 ? 50 ? 50 ? 50 ? 50 ? 4 5 8 7 1:1 tpfip tpfin vcct gnda 0.1 f .01 f 2 1 * = 0.001 f / 2.0 kv .01 f 1. the 100 ? transmit load termination resistor typica lly required is integrated in the lxt9785/ lxt9785e. 2. the 100 ? receive load termination resistor typically required is integrated in the lxt9785/
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 170 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 figure 36. recommended intel ? lxt9785/lxt9785e-to-3.3 v fiber transceiver interface circuitry lxt9785(e) tpfin n tpfip n tpfop n tpfon n to fiber network 3.3v fiber txcvr td - td + rd - rd + sd sd n +2.5v +2.5v +3.3v 130? 82? 50? 50? 27? 0.01 f ? 0.1 f 130? 130? 1 0.01 f 0.01 f +3.3v 0.01 f ? 0.1 f 2 k ?2 k ? 1.4 k ?1.3 k ? sd_2p5v gndpecl vccpecl 3.3v 1. refer to the transceiver manufacturers? recommendations for te rmination circuitry.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 171 document number: 249241 revision number: 007 revision date: august 28, 2003 figure 37. recommended intel ? lxt9785/lxt9785e-to-5 v fiber transceiver interface circuitry lxt9785(e) tpfin n tpfip n tpfop n tpfon n to fiber network 5v fiber txcvr td - td + rd - rd + sd sd n +2.5v +2.5v +2.5v 0.01 f 0.01 f 0.01 f ? 0.1 f 0.01 f ? 0.1 f 0.01 f 0.01 f on semiconductor* mc100lvel92 pecl-to-lvpecl logic translator 2 27? 50? 50? 127? 127? 118? 118? 270? 270? 1 +5v 3.1 k ? 3.1 k ? 1.15 k ?1.1 k ? 0.01 f ? 0.1 f sd_2p5v gndpecl vccpecl 3.3v 1. refer to the transceiver manufacturers? recommendations for termination circuitry. 2. see figure 38 on page 172 for recommended logic translator interface circuitry.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 172 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 figure 38. on semiconductor triple pecl-to-lvpecl translator vcc d0 __ d0 vbb pecl d1 __ d1 vbb pecl d2 __ d2 gnd vcc q0 __ q0 lvcc q1 __ q1 lvcc q2 __ q2 vcc 0.01 f 5v 0.01 f 3.3v lvpecl output signal (lxt9785) pecl input signal (5v fiber txcvr) 3.3v 130 ? 82 ? 5v 130 ? 82 ? on semiconductor* mc100lvel92 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 0.01 f 3.3v 130 ? 82 ?
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 173 document number: 249241 revision number: 007 revision date: august 28, 2003 6.0 test specifications note: table 51 through table 81 and figure 39 through figure 62 represent the target specifications of the lxt9785/lxt9785e. these specifications are not guaranteed and are subject to change without notice. minimum and maximum values listed in table 53 through table 81 apply over the recommended operating conditions specified in table 52 . table 51. intel ? lxt9785/lxt9785e absolute maximum ratings parameter sym min max units supply voltage v ccio , v cc pecl -0.3 4.0 v v cca , v ccd -0.3 3.0 v storage temperature t st -65 +150 oc caution: exceeding these values may cause perm anent damage. func tional operation under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 52. intel ? lxt9785/lxt9785e operating conditions (sheet 1 of 2) parameter sym min typ 1 (2.5 v ccio ) typ 1 (3.3 v ccio ) max units commercial operating temperature ambient t opa 0? ? 70oc case t opc 0 ? ? 108 oc extended operating temperature ambient t opa -40 85 oc case t opc -40 123 oc supply voltage 2 analog & digital vcca, vccd 2.38 2.5 2.5 2.63 v i/o vccio 2.38 2.5 3.3 3.46 v i/o (sd_2p5v = 0) vccpecl 3.14 n/a 3.3 3.46 v i/o (sd_2p5v = 1) 2.38 2.5 n/a 2.63 v operating current - rmii 3 100base-tx i cc ? 780 810 ma i ccio ? 60 130 160 ma 100base-fx i cc ? 380 410 ma i ccio ? 90 170 200 ma 10base-t i cc ? 710 765 ma i ccio ?30 70 90ma power-down mode hardware i cc ?20 20ma i ccio ?2 3 4ma auto-negotiation i cc ? 500 540 ma i ccio ?2 4 4ma 1. typical values are at 25 c and are for design ai d only; not guaranteed and not subject to production testing. 2. voltages with respect to gr ound unless otherwise specified. 3. values are aggregated for all eight ports.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 174 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 operating current - smii 3 100base-tx i cc ? 800 830 ma i ccio ? 70 130 160 ma 100base-fx i cc ? 380 410 ma i ccio ? 90 170 200 ma 10base-t i cc ? 740 770 ma i ccio ? 60 110 130 ma power-down mode hardware i cc ?50 50ma i ccio ?3 5 5ma auto-negotiation i cc ? 520 570 ma i ccio ?20 30 30ma operating current - ss-smii 3 100base-tx i cc ? 800 835 ma i ccio ? 90 170 200 ma 100base-fx i cc ? 380 410 ma i ccio ? 90 170 200 ma 10base-t i cc ? 740 780 ma i ccio ? 90 150 180 ma power-down mode hardware i cc ?30 40ma i ccio ?3 5 5ma auto-negotiation i cc ? 530 570 ma i ccio ?50 70 80ma table 53. intel ? lxt9785/lxt9785e digital i/o dc electric al characteristics (vccio = 2.5 v +/- 5%) parameter sym min typ 1 max units test conditions input low voltage v il ? ? 0.75 v ? input high voltage v ih 1.75 ? ? v ? input current i i -100 ? 100 a 0.0 < v i < v cc output low voltage v ol ??0.2v i ol = 4 ma output low voltage (led m _ n pins) v ol -led ? ? 0.5 v i ol = 10 ma output high voltage v oh 2.07 ? ? v i oh = -4 ma 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. table 52. intel ? lxt9785/lxt9785e operating conditions (sheet 2 of 2) parameter sym min typ 1 (2.5 v ccio ) typ 1 (3.3 v ccio ) max units 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. voltages with respect to ground unless otherwise specified. 3. values are aggregated for all eight ports.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 175 document number: 249241 revision number: 007 revision date: august 28, 2003 table 54. intel ? lxt9785/lxt9785e digital i/o dc electri cal characteristics (vccio = 3.3 v +/- 5%) parameter sym min typ 1 max units test conditions input low voltage v il ??0.8v ? input high voltage v ih 2.0 ? ? v ? input current i i -100 ? 100 a 0.0 < v i < v cc output low voltage v ol ??0.2v i ol = 4 ma output low voltage (led m _ n pins) v ol -led ? ? 0.5 v i ol = 10 ma output high voltage v oh 2.4 ? ? v i oh = -4 ma 1. typical values are at 25 c and are for design ai d only; not guaranteed and not subject to production testing. table 55. intel ? lxt9785/lxt9785e digital i/o dc el ectrical characteristics ? sd pins parameter sym min typ 1 max units test conditions 2.5 v operation input low voltage v il 0.69 0.8 1.03 v vccpecl = 2.5 v input high voltage v ih 1.34 1.6 1.62 v vccpecl = 2.5 v 3.3 v operation input low voltage v il 1.49 1.6 1.83 v vccpecl = 3.3 v input high voltage v ih 2.14 2.4 2.42 v vccpecl = 3.3 v 1. typical values are at 25 c and are for design ai d only; not guaranteed and not subject to production testing. 2. for 2.5 v operation, sd_2p5v = vccpecl and vccpecl=2.5 v. 3. for 3.3 v operation, sd_2p5v = gndpecl or floating and vccpecl=3.3 v. table 56. intel ? lxt9785/lxt9785e required clock characteristics parameter sym min typ 2 max units test conditions smii input frequency f ? 125 ? mhz ? rmii input frequency f ? 50 ? mhz ? input clock frequency tolerance 1 ? f ? ? 50 ppm ? input clock duty cycle 1 tdc 35 50 65 % rmii selection input clock duty cycle - refclk, txclk 1 tdc 40 50 60 % smii/ss-smii selection output rxclk duty cycle tdc 45 50 55 % ss-smii only 1. parameter is guaranteed by design; not subject to production testing. 2. typical values are at 25 c and are for design ai d only; not guaranteed and not subject to production testing.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 176 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 table 57. intel ? lxt9785/lxt9785e 100base-tx transceiver characteristics parameter sym min typ 1 max units test conditions peak differential output voltage v p 0.95 ? 1.05 v note 2 signal amplitude symmetry vss 98 ? 102 % note 2 signal rise/fall time t rf 3 ? 5 ns note 2 rise/fall time symmetry t rfs ? ? 0.5 ns note 2 duty cycle distortion ? ? ? +/- 0.5 ns offset from 16 ns pulse width at 50% of pulse peak overshoot v o ?? 5 % ? jitter magnitude (measured differentially) t tx-jit ??1.4ns ? 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. measured at the line side of the transformer, line replaced by 100 ? (+/-1%) resistor. table 58. intel ? lxt9785/lxt9785e 100base-fx transceiver characteristics parameter sym min typ 1 max units test conditions transmitter peak-to-peak differential output voltage v diffp - p 0.6 1.44 ? v ? signal rise/fall time t rf ? ? 1.8 ns note 2 jitter magnitude (measured differentially) t tx-jit ?? 1.4 ns ? receiver peak differential input voltage v ip 0.55 ? ? v ? common mode input range v cmir ??v cc - 0.5 v ? input low voltage (sd pins) v il v cc -1.84 v cc -1.63 v? input high voltage (sd pins) v ih v cc -1.04 v cc -0.88 v? 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. 20 - 80 percent into 100 ? equivalent load of a ty pical fiber transceiver.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 177 document number: 249241 revision number: 007 revision date: august 28, 2003 table 59. intel ? lxt9785/lxt9785e 10base-t transceiver characteristics parameter sym min typ 1 max units test conditions transmitter peak differential output voltage v op 2.2 2.5 2.8 v note 2 link transmit period ? 8 ? 24 ms ? jitter magnitude added by the mau and pls sections 3, 4 t tx-jit ??11 ns ? receiver receive input impedance 3 z in ?100? w between tpfip and tpfin link min receive timer tlr min 2?7 ms ? link max receive timer tlr max 50 ? 150 ms ? differential squelch threshold v ds ?475?mv peak 5 mhz square wave input 1. typical values are at 25 c and are for design ai d only; not guaranteed and not subject to production testing. 2. parameter is guaranteed by design; not subject to production testing. 3. ieee 802.3 specifies maximum jitter addition at 1.5 ns for the aui cable, 0.5 ns from the encoder, and 3.5 ns from the mau. 4. after line model specified by ieee 802.3 for 10base-t mau.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 178 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 figure 39. intel ? lxt9785/lxt9785e smii - 100base-tx receive timing table 60. intel ? lxt9785/lxt9785e smii - 100base-tx receive timing parameters parameter sym min typ 1 max units test conditions rxdata output delay from refclk rising edge t1 1.5 ? 5 ns minimum c l = 5 pf maximum c l = 20 pf rxdata rise/fall time t2 ? 1.0 ? ns ? receive start of /j/ to crs asserted t3 ? 21 29 bt 2 synchronous sampling of smii receive start of /t/ to crs de- asserted t4 ? 25 30 bt 2 synchronous sampling of smii sync setup to refclk rising edge t5 1.5 ? ? ns ? sync hold from refclk rising edge t6 1.0 ? ? ns ? 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. ?bt? signifies bit times at the line rate (that is, bt = 100 ns if using 10base-t, bt = 10 ns if using 100base-tx or 100base-fx). note: the table latency values are derived with the har dware configuration pins fifosel[1:0] set at a default configuration of 00 (32 bits of initial fill). refclk rxdata tpfi t 3 t 1 t 2 t 4 t 6 t 5 sync
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 179 document number: 249241 revision number: 007 revision date: august 28, 2003 figure 40. intel ? lxt9785/lxt9785e smii - 100base-tx transmit timing table 61. intel ? lxt9785/lxt9785e smii - 100base-tx transmit timing parameters parameter sym min typ 1 max units test conditions sync setup to refclk rising edge and txdata setup to refclk rising edge t1 1.5 ? ? ns ? sync hold from refclk rising edge and txdata hold from refclk rising edge t2 1.0 ? ? ns ? txen sampled to start of /j/ t3 ? 11 18 bt 2 ? 1. typical values are at 25 c and are for design ai d only; not guaranteed and not subject to production testing. 2. ?bt? signifies bit times at the line rate (that is , bt = 100 ns if using 10base-t, bt = 10 ns if using 100base-tx or 100base-fx). note: the table latency values are derived with the hard ware configuration pins fifosel[1:0] set at a default configuration of 00 (32 bits of initial fill). txdata tpfo t 1 t 2 t 3 sync t 1 t 2 refclk
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 180 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 figure 41. intel ? lxt9785/lxt9785e smii - 100base-fx receive timing table 62. intel ? lxt9785/lxt9785e smii - 100base-fx receive timing parameters parameter sym min typ 1 max units test conditions rxdata output delay from refclk rising edge t1 1.5 ? 5 ns minimum c l = 5 pf maximum c l = 20 pf rxdata rise/fall time t2 ? 1 ? ns ? receive start of /j/ to crs asserted t3 ? 18 26 bt 2 synchronous sampling of smii receive start of /t/ to crs de- asserted t4 ? 23 27 bt 2 synchronous sampling of smii sync setup to refclk rising edge t5 1.5 ? ? ns ? sync hold from refclk rising edge t6 1.0 ? ? ns ? 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. ?bt? signifies bit times at the line rate (that is, bt = 100 ns if using 10base-t, bt = 10 ns if using 100base-tx or 100base-fx). note: the table latency values are derived with the har dware configuration pins fifosel[1:0] set at a default configuration of 00 (32 bits of initial fill). refclk rxdata tpfi t 3 t 1 t 2 t 4 t 6 t 5 sync
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 181 document number: 249241 revision number: 007 revision date: august 28, 2003 figure 42. intel ? lxt9785/lxt9785e smii - 100base-fx transmit timing table 63. intel ? lxt9785/lxt9785e smii - 100base-fx transmit timing parameters parameter sym min typ 1 max units test conditions sync setup to refclk rising edge and txdata setup to refclk rising edge t1 1.5 ? ? ns ? sync hold from refclk rising edge and txdata hold from refclk rising edge t2 1.0 ? ? ns ? txen sampled to start of /j/ t3 ? 10 17 bt 2 1. typical values are at 25 c and are for design ai d only; not guaranteed and not subject to production testing. 2. ?bt? signifies bit times at the line rate (that is , bt = 100 ns if using 10base-t, bt = 10 ns if using 100base-tx or 100base-fx). note: the table latency values are derived with the hard ware configuration pins fifosel[1:0] set at a default configuration of 00 (32 bits of initial fill). txdata tpfo t 1 t 2 t 3 sync t 1 t 2 refclk
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 182 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 figure 43. intel ? lxt9785/lxt9785e smii - 10base-t receive timing table 64. intel ? lxt9785/lxt9785e smii - 10base-t receive timing parameters parameter sym min typ 1 max units test conditions rxdata output delay from refclk rising edge t1 1.5 ? 5 ns minimum c l = 5 pf maximum c l = 20 pf rxdata rise/fall time t2 ? 1 ? ns ? receive start-of-frame to crs asserted t3 ? 17 21 bt 3 synchronous sampling of smii 2 receive start-of-idle to crs de-asserted t4 ? 17 18 bt 3 synchronous sampling of smii 2 sync setup to refclk rising edge t5 1.5 ? ? ns ? sync hold from refclk rising edge t6 1.0 ? ? ns ? 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. assumes each smii segment is sampled for crs. 3. ?bt? signifies bit times at the line rate (that is, bt = 100 ns if using 10base-t, bt = 10 ns if using 100base-tx or 100base-fx). note: the table latency values are derived with the har dware configuration pins fifosel[1:0] set at a default configuration of 00 (32 bits of initial fill). refclk rxdata tpfi t 3 t 1 t 2 t 4 t 6 t 5 sync
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 183 document number: 249241 revision number: 007 revision date: august 28, 2003 figure 44. intel ? lxt9785/lxt9785e smii - 10base-t transmit timing table 65. intel ? lxt9785/lxt9785e smii-10base-t transmit timing parameters parameter sym min typ 1 max units test conditions sync setup to refclk rising edge and txdata setup to refclk rising edge t1 1.5 ? ? ns ? sync hold to refclk rising edge and txdata hold from refclk rising edge t2 1.0 ? ? ns ? txen sampled to start-of-frame t3 ? 10 14 bt 2 ? 1. typical values are at 25 c and are for design ai d only; not guaranteed and not subject to production testing. 2. ?bt? signifies bit times at the line rate (that is , bt = 100 ns if using 10base-t, bt = 10 ns if using 100base-tx or 100base-fx). note: the table latency values are derived with the hard ware configuration pins fifosel[1:0] set at a default configuration of 00 (32 bits of initial fill). txdata tpfo t 1 t 2 t 3 sync t 1 t 2 refclk
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 184 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 figure 45. intel ? lxt9785/lxt9785e ss-smii - 100base-tx receive timing table 66. intel ? lxt9785/lxt9785e ss-smii - 100ba se-tx receive timing parameters parameter sym min typ 1 max units test conditions refclk rising edge to rxclk rising edge t1 ? 1.5 ? ns ? rxdata/rxsync output delay from rxclk rising edge t2 1.5 ? 5 ns minimum c l = 5pf maximum c l = 40pf rxdata/rxsync rise/fall time t3 ? 1.0 ? ns ? receive start of /j/ to crs asserted t4 ? 21 27 bt 2 ? receive start of /t/ to crs de-asserted t5 ? 25 30 bt 2 ? 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. ?bt? signifies bit times at the line rate (that is, bt = 100 ns if using 10base-t, bt = 10 ns if using 100base-tx or 100base-fx). note: the table latency values are derived with the har dware configuration pins fifosel[1:0] set at a default configuration of 00 (32 bits of initial fill). t 2 rxclk refclk t 1 rxdata tpfi t 4 t 3 t 5 rxsync t 3 t 3
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 185 document number: 249241 revision number: 007 revision date: august 28, 2003 figure 46. intel ? lxt9785/lxt9785e ss-smii - 100base-tx transmit timing table 67. intel ? lxt9785/lxt9785e ss-smii - 100base-tx transmit timing parameter sym min typ 1 max units test conditions txsync setup to txclk rising edge and txdata setup to txclk rising edge t1 1.5 ? ? ns ? txsync hold from txclk rising edge and txdata hold to txclk rising edge t2 1.0 ? ? ns ? txen sampled to start of /j/ t3 ? 11 18 bt 2 ? 1. typical values are at 25 c and are for design ai d only; not guaranteed and not subject to production testing. 2. ?bt? signifies bit times at the line rate (that is , bt = 100 ns if using 10base-t, bt = 10 ns if using 100base-tx or 100base-fx). note: the table latency values are derived with the hard ware configuration pins fifosel[1:0] set at a default configuration of 00 (32 bits of initial fill). txdata tpfo t 1 t 2 t 3 txsync t 1 t 2 txclk
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 186 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 figure 47. intel ? lxt9785/lxt9785e ss-smii - 100base-fx receive timing table 68. intel ? lxt9785/lxt9785e ss-smii - 100ba se-fx receive timing parameters parameter sym min typ 1 max units test conditions refclk rising edge to rx clk rising edge t1 ? 1.5 ns ? rxdata/rxsync output delay from rxclk rising edge t2 1.5 ? 5 ns minimum c l = 5pf maximum c l = 40pf rxdata/rxsync rise/fall time t3 ? 1 ? ns ? receive start of /j/ to crs asserted t4 ? 18 23 bt 2 ? receive start of /t/ to crs de-asserted t5 ? 21 26 bt 2 ? 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. ?bt? signifies bit times at the line rate (that is, bt = 100 ns if using 10base-t, bt = 10 ns if using 100base-tx or 100base-fx). note: the table latency values are derived with the har dware configuration pins fifosel[1:0] set at a default configuration of 00 (32 bits of initial fill). t 2 rxclk refclk t 1 rxdata tpfi t 4 t 3 t 5 rxsync t 3 t 3
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 187 document number: 249241 revision number: 007 revision date: august 28, 2003 figure 48. intel ? lxt9785/lxt9785e ss-smii - 100base-fx transmit timing table 69. intel ? lxt9785/lxt9785e ss-smii - 100base-fx transmit timing parameters parameter sym min typ 1 max units test conditions txsync setup to txclk rising edge and txdata setup to txclk rising edge t1 1.5 ? ? ns ? txsync hold from txclk rising edge and txdata hold to txclk rising edge t2 1.0 ? ? ns ? txdata to tpfo latency t3 ? 11 13 bt 2 ? 1. typical values are at 25 c and are for design ai d only; not guaranteed and not subject to production testing. 2. ?bt? signifies bit times at the line rate (that is , bt = 100 ns if using 10base-t, bt = 10 ns if using 100base-tx or 100base-fx). note: the table latency values are derived with the hard ware configuration pins fifosel[1:0] set at a default configuration of 00 (32 bits of initial fill). txdata tpfo t 1 t 2 t 3 txsync t 1 t 2 txclk
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 188 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 figure 49. intel ? lxt9785/lxt9785e ss-smii - 10base-t receive timing table 70. intel ? lxt9785/lxt9785e ss-smii - 10base-t receive timing parameters parameter sym min typ 1 max units test conditions refclk rising edge to rxclk rising edge t1 ? 1.5 ? ns ? rxdata/rxsync output delay from rxclk rising edge t2 1.5 ? 5 ns minimum c l = 5pf maximum c l = 40pf rxdata/rxsync rise/fall time t3 ? 1 ? ns ? receive start-of-frame to crs asserted t4 ? 10 11 bt 3 synchronous sampling of smii 2 receive start-of-idle to crs de-asserted t5 ? 18 21 bt 3 synchronous sampling of smii 2 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. assumes each smii segment is sampled for crs. 3. ?bt? signifies bit times at the line rate (that is, bt = 100 ns if using 10base-t, bt = 10 ns if using 100base-tx or 100base-fx). note: the table latency values are derived with the har dware configuration pins fifosel[1:0] set at a default configuration of 00 (32 bits of initial fill). t 2 rxclk refclk t 1 rxdata tpfi t 4 t 3 t 5 rxsync
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 189 document number: 249241 revision number: 007 revision date: august 28, 2003 figure 50. intel ? lxt9785/lxt9785e ss-smii - 10base-t transmit timing table 71. intel ? lxt9785/lxt9785e ss-smii - 10base-t transmit timing parameters parameter sym min typ 1 max units test conditions txsync setup to txclk rising edge and txdata setup to txclk rising edge t1 1.5 ? ? ns ? txsync hold to txclk rising edge and txdata hold from txclk rising edge t2 1.0 ? ? ns ? txdata to tpfo latency t3 ? 10 14 bt 2 ? 1. typical values are at 25 c and are for design ai d only; not guaranteed and not subject to production testing. 2. ?bt? signifies bit times at the line rate (that is , bt = 100 ns if using 10base-t, bt = 10 ns if using 100base-tx or 100base-fx). note: the table latency values are derived with the hard ware configuration pins fifosel[1:0] set at a default configuration of 00 (32 bits of initial fill). txdata tpfo t 1 t 2 t 3 txsync t 1 t 2 txclk
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 190 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 figure 51. intel ? lxt9785/lxt9785e rmii - 100base-tx receive timing table 72. intel ? lxt9785/lxt9785e rmii - 100base-tx receive timing parameters parameter sym min typ 1 max units test conditions rxdata<1:0>, crs_dv, rxer setup to refclk rising edge 3 t1 4 ? 14 ns ? rxdata<1:0>, crs_dv, rxer hold from refclk rising edge 3 t2 2 ? 14 ns ? receive start of /j/ to crs_dv asserted t3 ? 16 21 bt 2 ? receive start of /t/ to crs_dv de-asserted t4 ? 20 27 bt 2 ? 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. ?bt? signifies bit times at the line rate (that is, bt = 100 ns if using 10base-t, bt = 10 ns if using 100base-tx or 100base-fx). 3. values and conditions from rmii specification, rev. 1.2. note: the table latency values are derived with the har dware configuration pins fifosel[1:0] set at a default configuration of 00 (32 bits of initial fill). refclk rxdata[1:0] tpfi t 1 t 2 t 3 crs_dv t 4
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 191 document number: 249241 revision number: 007 revision date: august 28, 2003 figure 52. intel ? lxt9785/lxt9785e rmii - 100base-tx transmit timing table 73. intel ? lxt9785/lxt9785e rmii - 100base-tx transmit timing parameters parameter sym min typ 1 max units test conditions txdata<1:0>/txen setup to refclk rising edge t1 4 ? ? ns ? txdata<1:0>/txen hold from refclk rising edge t2 2 ? ? ns ? txen sampled to tpfo out (tx latency) t3 ? 12 17 bt 2 ? 1. typical values are at 25 c and are for design ai d only; not guaranteed and not subject to production testing. 2. ?bt? signifies bit times at the line rate (that is , bt = 100 ns if using 10base-t, bt = 10 ns if using 100base-tx or 100base-fx). note: the table latency values are derived with the hard ware configuration pins fifosel[1:0] set at a default configuration of 00 (32 bits of initial fill). refclk txdata(1:0) tpfo t 3 t 1 t 2 txen t 1 t 2
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 192 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 figure 53. intel ? lxt9785/lxt9785e rmii - 100base-fx receive timing table 74. intel ? lxt9785/lxt9785e rmii - 100base-fx receive timing parameters parameter sym min typ 1 max units test conditions rxdata<1:0>, crs_dv, rxer setup to refclk rising edge 3 t1 4 ? 14 ns ? rxdata<1:0>, crs_dv, rxer hold from refclk rising edge 3 t2 2 ? 14 ns ? receive start of /j/ to crs_dv asserted t3 ? 14 18 bt 2 ? receive start of /t/ to crs_dv de-asserted t4 ? 18 25 bt 2 ? 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. ?bt? signifies bit times at the line rate (that is, bt = 100 ns if using 10base-t, bt = 10 ns if using 100base-tx or 100base-fx). 3. values and conditions from rmii specification, rev. 1.2. note: the table latency values are derived with the har dware configuration pins fifosel[1:0] set at a default configuration of 00 (32 bits of initial fill). refclk rxdata[1:0] tpfi t 1 t 2 t 3 crs_dv t 4
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 193 document number: 249241 revision number: 007 revision date: august 28, 2003 figure 54. intel ? lxt9785/lxt9785e rmii - 100base-fx transmit timing table 75. intel ? lxt9785/lxt9785e rmii - 100base-fx transmit timing parameters parameter sym min typ 1 max units test conditions txdata<1:0>/txen setup to refclk rising edge t1 4 ? ? ns ? txdata<1:0>/tx-en hold from refclk rising edge t2 2 ? ? ns ? txen sampled to tpfo out (tx latency) t3 ? 10 12 bt 2 ? 1. typical values are at 25 c and are for design ai d only; not guaranteed and not subject to production testing. 2. ?bt? signifies bit times at the line rate (that is , bt = 100 ns if using 10base-t, bt = 10 ns if using 100base-tx or 100base-fx). note: the table latency values are derived with the hard ware configuration pins fifosel[1:0] set at a default configuration of 00 (32 bits of initial fill). refclk txdata(1:0) tpfo t 3 t 1 t 2 txen t 1 t 2
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 194 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 figure 55. intel ? lxt9785/lxt9785e rmii - 10base-t receive timing table 76. intel ? lxt9785/lxt9785e rmii - 10base-t receive timing parameters parameter sym min typ 1 max units test conditions rxdata<1:0>, crs_dv setup to refclk rising edge 3 t1 4 ? 14 ns ? rxdata<1:0>, crs_dv hold from refclk rising edge 3 t2 2 ? 14 ns ? tpfi in to crs_dv asserted t3 1.5 3 4 bt 2 ? tpfi quiet to crs_dv de-asserted t4 12 15 16 bt 2 ? 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. ?bt? signifies bit times at the line rate (that is, bt = 100 ns if using 10base-t, bt = 10 ns if using 100base-tx or 100base-fx). 3. values and conditions from rmii specification, rev. 1.2. note: the table latency values are derived with the har dware configuration pins fifosel[1:0] set at a default configuration of 00 (32 bits of initial fill). refclk rxdata[1:0] tpfi t 1 t 2 t 3 crs_dv t 4
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 195 document number: 249241 revision number: 007 revision date: august 28, 2003 figure 56. intel ? lxt9785/lxt9785e rmii - 10base-t transmit timing table 77. intel ? lxt9785/lxt9785e rmii - 10base-t transmit timing parameters parameter sym min typ 1 max units test conditions txdata<1:0>/txen setup to refclk rising edge t1 4 ? ? ns ? txdata<1:0>/txen hold from refclk rising edge t2 2 ? ? ns ? txen sampled to tpfo out (tx latency) t3 ? 8.5 14 bt 2 ? 1. typical values are at 25 c and are for design ai d only; not guaranteed and not subject to production testing. 2. ?bt? signifies bit times at the line rate (that is , bt = 100 ns if using 10base-t, bt = 10 ns if using 100base-tx or 100base-fx). note: the table latency values are derived with the hard ware configuration pins fifosel[1:0] set at a default configuration of 00 (32 bits of initial fill). refclk txdata(1:0) tpfo t 3 t 1 t 2 txen t 1 t 2
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 196 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 figure 57. intel ? lxt9785/lxt9785e auto-negotiation and fast link pulse timing figure 58. intel ? lxt9785/lxt9785e fast link pulse timing table 78. intel ? lxt9785/lxt9785e auto-negotiation and fast link pulse timing parameters parameter sym min typ 1 max units test conditions clock/data pulse width t1 ? 100 ? ns ? clock pulse to data pulse t2 55.5 ? 69.5 s? clock pulse to clock pulse t3 111 ? 139 s? flp burst width t4 ? 2 ? ms ? flp burst to flp burst t5 8 ? 24 ms ? clock/data pulses per burst ? 17 ? 33 ea ? 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. tpfop t1 t1 t2 t3 clock pulse data pulse clock pulse tpfop t4 t5 flp burst flp burst
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 197 document number: 249241 revision number: 007 revision date: august 28, 2003 figure 59. intel ? lxt9785/lxt9785e mdio write timing (mdio sourced by mac) figure 60. intel ? lxt9785/lxt9785e mdio read timing (mdio sourced by phy) table 79. intel ? lxt9785/lxt9785e mdio timing parameters parameter sym min typ 1 max units test conditions mdio setup before mdc, sourced by sta t1 10 ? ? ns ? mdio hold after mdc, sourced by sta t2 10 ? ? ns ? mdc to mdio output delay, sourced by phy t3 0 ? 40 ns ? 1. typical values are at 25 c and are for design ai d only; not guaranteed and not subject to production testing. t1 mdc mdio t2 t3 mdc mdio
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 198 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 figure 61. intel ? lxt9785/lxt9785e power-up timing table 80. intel ? lxt9785/lxt9785e powe r-up timing parameters parameter sym min typ 1 max units test conditions voltage threshold v1 2.1 ? ? v ? power-up recovery time t pdr 100 ? ? ms ? software power-down 2 t spdr 20 ? ? ms ? 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. the minimum time required between bringing up consec utive ports powered down by register bit 0.11, or a software or hardware reset. figure 62. intel ? lxt9785/lxt9785e reset recovery timing table 81. intel ? lxt9785/lxt9785e reset recovery timing parameters parameter sym min typ 1 max units test conditions reset pulse width tpw 10 ? ? ns ? reset recovery delay trcdly 0.4 ? ? ms ? 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. vcc mdio,etc v1 tpdr reset mdio,etc tpw trcdly
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 199 document number: 249241 revision number: 007 revision date: august 28, 2003 7.0 register definitions the lxt9785/lxt9785e register set includes multi ple 16-bit registers, 18 registers per port. table 82 presents a complete register listing. table 83, ?control register (address 0)? on page 200 through table 100, ?cable diagnostics register (address 29, hex 1d)? on page 217 define individual registers and table 101, ?intel? lxt9785/lxt9785e register bit map? on page 219 provides a consolidated me mory map of all registers. base registers (0 through 8) are defined in accordance with the ?reconciliation sublayer and media independent interface? an d ?physical layer link signaling for 10/100 mbps auto- negotiation? sections of the ieee 802.3 standard. additional registers (16 th rough 21, 25, 27, and 29) are define d in accordance with the ieee 802.3 standard for adding unique chip functions. the bga15 package on some registers has differ ent default values. some lxt9785 features are not available on the bga15 package. these differ ences are called out in the register description and in the table notes in individual register tables. table 82. intel ? lxt9785/lxt9785e register set (sheet 1 of 2) address register name bit assignments 0 ?control register (address 0)? refer to table 83 on page 200 1 ?status register (address 1)? refer to table 84 on page 201 2 ?phy identification register 1 (address 2)? refer to table 85 on page 203 3 ?phy identification register 2 (address 3)? refer to table 86 on page 203 4 ?auto-negotiation advertisement register (address 4)? refer to table 87 on page 204 5 ?auto-negotiation link partner base page ability register (address 5)? refer to table 88 on page 205 6 ?auto-negotiation expansion register (address 6)? refer to table 89 on page 206 7 ?auto-negotiation next page tr ansmit register (address 7)? refer to table 90 on page 206 8 ?auto-negotiation link partner next page receive register (address 8)? refer to table 91 on page 207 9 1000base-t/100base-t2 control not implemented 10 1000base-t/100base-t2 status not implemented 15 extended status not implemented 16 ?port configuration register (address 16, hex 10)? refer to table 92 on page 207 17 ?quick status register (address 17, hex 11)? refer to table 93 on page 209 18 ?interrupt enable register (address 18, hex 12)? refer to table 94 on page 211 19 ?interrupt status register (address 19, hex 13)? refer to table 95 on page 212 20 ?led configuration register (address 20, hex 14)? refer to table 96 on page 213 21 ?receive error count register (address 21, hex 15)? refer to table 97 on page 214 22-24 reserved n/a 25 ?rmii out-of-band signaling register (address 25, hex 19)? refer to table 98 on page 215 26 reserved n/a
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 200 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 27 ?trim enable register (address 27, hex 1b)? refer to table 99 on page 216 28 reserved n/a 29 ?cable diagnostics register (address 29, hex 1d)? refer to table 100 on page 217 30 - 31 reserved n/a table 83. control register (address 0) (sheet 1 of 2) bit name description type 1 default 15 reset 0 = normal operation 1 = phy reset r/w sc 0 2 14 loopback 0 = disable loopback mode 1 = enable loopback mode not recommended to enable auto-negotiation while in internal loopback operation. r/w 0 13 speed selection 0.6 1 1 0 0 0.13 1 = reserved 0 = 1000 mbps (not allowed) 1 = 100 mbps 0 = 10 mbps r/w lshr 3,4 12 auto-negotiation enable 0 = disable auto-negotiation process 1 = enable auto-negotiation process r/w lshr 3,4 11 power-down 0 = normal operation 1 = power-down r/w lshr 3,5 10 isolate 0 = normal operation 1 = electrically isolate phy from rmii/smii/ss- smii interfaces r/w 0 9 restart auto-negotiation 0 = normal operation 1 = restart auto-negotiation process r/w sc 0 8 duplex mode 0 = half-duplex 1 = full-duplex r/w lshr 3,4 1. r/w = read/write, sc = self clearing when operation complete. 2. during a hardware reset, all lhr information is latched in from the pins. during a software reset (0.15), the lshr information is not re-read from the pins. this in formation reverts back to the information that was read in during the hardware reset. during a hardware re st, register information is unavailable from 1 ms after de-assertion of the reset. during a software rese t (0.15) the registers are available for reading. the reset bit should be polled to see when the part has completed reset. 3. lshr = default value is derived from a single device input pin state or a group of device input pin states as the pin(s) are latched at startup or hardware reset. 4. default value of register bits 0.12, 0.13, and 0.8 are determined by the cfg pins as described in table 42, ?intel? lxt9785/9785e global hardware configuration settings? on page 129 . 5. default value of register bit 0.11 is det ermined by the linkhold configuration pin. table 82. intel ? lxt9785/lxt9785e register set (sheet 2 of 2) address register name bit assignments
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 201 document number: 249241 revision number: 007 revision date: august 28, 2003 7 collision test this bit is ignored by the lxt9785/lxt9785e 0 = disable col signal test 1 = enable col signal test r/w 0 6 speed selection 1000 mbps 0.6 1 1 0 0 0.13 1 = reserved 0 = 1000 mbps (not allowed) 1 = 100 mbps 0 = 10 mbps r/w 0 5:0 reserved write as 0, ignore on read r/w 000000 table 84. status register (address 1) bit name description type 1,2 default 15 100base-t4 0 = phy not able to perform 100base-t4 1 = phy able to perform 100base-t4 r0 14 100base-x full-duplex 0 = phy not able to perform full-duplex 100base-x 1 = phy able to perform full-duplex 100base-x r1 13 100base-x half-duplex 0 = phy not able to perform half-duplex 100base-x 1 = phy able to perform half-duplex 100base-x r1 12 10 mbps full-duplex 0 = phy not able to operate at 10 mbps in full-duplex mode 1 = phy able to operate at 10 mbps in full-duplex mode r1 11 10 mbps half-duplex 0 = phy not able to operate at 10 mbps in half-duplex 1 = phy able to operate at 10 mbps in half-duplex mode r1 10 100base-t2 full-duplex 0 = phy not able to perfo rm full-duplex 100base-t2 1 = phy able to perform full-duplex 100base-t2 r0 9 100base-t2 half-duplex 0 = phy not able to perform half-duplex 100base-t2 1 = phy able to perform half-duplex 100base-t2 r0 8 extended status 0 = no extended status information in register 15 1 = extended status information in register 15 r0 7 reserved write as 0, ignore on read r 0 6 mf preamble suppression 0 = phy will not accept management frames with preamble suppressed 1 = phy accepts management frames with preamble suppressed r0 1. r = read only 2. bits that latch high (lh) or latch low (ll) automatically clear when read. table 83. control register (address 0) (sheet 2 of 2) bit name description type 1 default 1. r/w = read/write, sc = self clearing when operation complete. 2. during a hardware reset, all lhr information is latched in from the pins. during a software reset (0.15), the lshr information is not re-read from the pins. this information reverts back to the information that was read in during the hardware reset. during a hardware re st, register information is unavailable from 1 ms after de-assertion of the reset. during a software rese t (0.15) the registers are available for reading. the reset bit should be polled to see when the part has completed reset. 3. lshr = default value is derived from a single device in put pin state or a group of device input pin states as the pin(s) are latched at startup or hardware reset. 4. default value of register bits 0.12, 0.13, and 0.8 are determined by the cf g pins as described in table 42, ?intel? lxt9785/9785e global hardware configuration settings? on page 129 . 5. default value of register bit 0.11 is det ermined by the linkhold configuration pin.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 202 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 5 auto-negotiation complete 0 = auto-negotiation not complete 1 = auto-negotiation complete r0 4 remote fault 0 = no remote fault condition detected 1 = remote fault condition detected r/ll 0 3 auto-negotiation ability 0 = phy is not able to perform auto-negotiation 1 = phy is able to perform auto-negotiation r1 2 link status 0 = link is down 1 = link is up r/ll 0 1 jabber detect 0 = jabber condition not detected 1 = jabber condition detected r/lh 0 0 extended capability 0 = basic register capabilities 1 = extended register capabilities r1 table 84. status register (address 1) bit name description type 1,2 default 1. r = read only 2. bits that latch high (lh) or latch low (ll) automatically clear when read.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 203 document number: 249241 revision number: 007 revision date: august 28, 2003 table 85. phy identification register 1 (address 2) bit name description type 1 default 15:0 phy id number the phy identifier composed of bits 3 through 18 of the oui r 0013 hex 1. r = read only table 86. phy identification register 2 (address 3) bit name description type 1 default 15:10 phy id number the phy identifier composed of bits 19 through 24 of the oui r 011110 9:4 manufacturer?s model number 6 bits containing manufacturer?s part number r 001111 3:1 manufacturer?s revision number 3 bits containing manufacturer?s revision number r xxx 2 0 model variant 0 = lxt9785 1 = lxt9785/lxt9785e rx 2 1. r = read only 2. refer to the identification information section in the intel ? lxt9785/lxt9785e specification update. figure 63. phy identifier bit mapping a bc 1 23 organizationally unique identifier rs 18 19 0 00 0 00 0 00 0 01 0 01 15 0 1 phy id register #1 (address 2) x 24 0 11 1 10 9 4 3 15 0 x phy id register #2 (address 3) 10 0 i/g 5 0 manufacturer's model number 3 0 0 0013 0 002b7 xxx xxxxxx 7b 20 00 the intel oui is 00207b hex. model variant 1 revision number
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 204 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 table 87. auto-negotiation advertisement register (address 4) bit name description type 1 default 15 next page 0 = port has no ability to send manual next pages 1 = port has ability to send manual next pages note: this bit should only be set to manually control the auto- negotiation process. it is not needed and should be cleared for dte discovery. r/w 0 14 reserved write as 0, ignore on read r 0 13 6 remote fault 0 = no remote fault 1 = remote fault r/w 0 12 reserved write as 0, ignore on read r/w 0 11 asymmetric pause pause operation defined in clause 40 and 27 0 = port is not pause capable 1 = port can only send pause r/w 0 10 pause 5 0 = pause operation disabled 1 = port can send and receive pause note: default for the bga15 package is 0. r/w lshr 2,3 9 100base-t4 0 = 100base-t4 capability is not available 1 = 100base-t4 capability is available (the lxt9785/lxt9785e does not support 100base-t4 but allows this bit to be set to advertise in the auto-negotiation sequence for 100base-t4 operation. an external 100base-t4 transceiver could be switched in if this capability is desired.) r/w 0 8 100base-tx full-duplex 0 = port is not 100base-t x full-duplex capable. 1 = port is 100base-tx full-duplex capable r/w lshr 2,4 7 100base-tx half-duplex 0 = port is not 100base-tx half-duplex capable 1 = port is 100base-tx half-duplex capable r/w lshr 2,4 6 10base-t full-duplex 0 = port is not 10base-t full-duplex capable 1 = port is 10base-t full-duplex capable r/w lshr 2,4 5 10base-t half-duplex 0 = port is not 10base-t half-duplex capable 1 = port is 10base-t half-duplex capable r/w lshr 2,4 4:0 selector field, s<4:0> <00001> = ieee 802.3 <00010> = ieee 802.9 islan-16t <00000> = reserved for future auto-negotiation development <11111> = reserved for future auto-negotiation development unspecified or reserved combinations should not be transmitted r/w 00001 1. r/w = read/write, r = read only 2. lshr = default value is derived from a single device input pin state or a group of device input pin states as the pin(s) are latched at startup or hardware reset. 3. the default setting of register bit 4.10 is determi ned by the pause pin. the bga15 package does not have a pause hardware configurat ion pin and has a default of 0. 4. default settings for bits 4.5:8 are determined by cfg pins as described in table 42, ?intel? lxt9785/ 9785e global hardware configuration settings? on page 129 . 5. pause operation is only valid for full-duplex modes. 6. if register bit 4.13 is set to advertise a fault, register bit 1.4 will be set. note: restart the auto-negotiation process whenev er register 4 is written/modified.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 205 document number: 249241 revision number: 007 revision date: august 28, 2003 table 88. auto-negotiation link partner base page ability register (address 5) bit name description type 1 default 2 15 next page 0 = link partner has no ability to send multiple pages 1 = link partner has ability to send multiple pages r0 14 acknowledge 0 = link partner has not received link code word from the the lxt9785/lxt9785e 1 = link partner has received link code word from the lxt9785/lxt9785e. r0 13 remote fault 0 = no remote fault 1 = remote fault r0 12 reserved write as 0, ignore on read r 0 11 asymmetric pause pause operation defined in clause 40 and 27 0 = link partner is not pause capable 1 = link partner can only send pause r0 10 pause 0 = link partner is not pause capable 1 = link partner can send and receive pause r0 9 100base-t4 0 = link partner is not 100base-t4 capable 1 = link partner is 100base-t4 capable r0 8 100base-tx full-duplex 0 = link partner is not 100base-tx full-duplex capable 1 = link partner is 100base-tx full-duplex capable r0 7 100base-tx 0 = link partner is not 100base-tx capable 1 = link partner is 100base-tx capable r0 6 10base-t full-duplex 0 = link partner is not 10base-t full-duplex capable 1 = link partner is 10base-t full-duplex capable r0 5 10base-t 0 = link partner is not 10base-t capable 1 = link partner is 10base-t capable r0 4:0 selector field s<4:0> <00001> = ieee 802.3 <00010> = ieee 802.9 islan-16t <00000> = reserved for future auto-negotiation development <11111> = reserved for future auto- negotiation development unspecified or reserved combinat ions shall not be transmitted r 00000 1. r = read only 2. default value at the start of auto-negotiation code word transmission.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 206 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 table 89. auto-negotiation expansion register (address 6) bit name description type 1 default 15:5 reserved write as 0, ignore on read r 0x000 4 parallel detection fault 0 = parallel detection fault has not occurred 1 = parallel detection fault has occurred r/ lh 0 3 link partner next page able 0 = link partner is not next page able 1 = link partner is next page able r0 2 next page able 0 = local device is not next page able 1 = local device is next page able r1 1 page received indicates that a new page has been received and the received code word has been loaded into register 5 or register 8 as specifi ed in clause 28 of 802.3. 0 = three identical and consec utive link code words have not been received from link partner 1 = three identical and consec utive link code words have been received from link partner r/ lh 0 0 link partner a/n able 0 = link partner is not auto-negotiation able 1 = link partner is auto-negotiation able r0 1. r = read only, lh = latching high ? cleared when read table 90. auto-negotiation next page transmit register (address 7) bit name description type 1 default 15 next page (np) 0 = last page 1 = additional next pages follow r/w 0 14 reserved write as 0, ignore on read. r 0 13 message page (mp) 0 = unformatted page 1 = message page r/w 1 12 acknowledge 2 (ack2) 0 = cannot comply with message 1 = complies with message r/w 0 11 toggle (t) 0 = previous value of the transmitted link code word equalled logic one 1 = previous value of the transmitted link code word equalled logic zero r0 10:0 message/ unformatted code field mp = 0: code interpreted as ?unformatted page? mp = 1: code interpreted as ?message page? r/w 0000000 0001 1. r/w = read write, r = read only
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 207 document number: 249241 revision number: 007 revision date: august 28, 2003 table 91. auto-negotiation link partner next page receive register (address 8) bit name description type 1 default 2 15 next page (np) 0 = link partner has no additional next pages to send 1 = link partner has additional next pages to send r0 14 acknowledge (ack) 0 = link partner has not received link code word from the lxt9785/lxt9785e 1 = link partner has received link code word from the lxt9785/lxt9785e r0 13 message page (mp) 0 = page sent by the link partner is an unformatted page 1 = page sent by the link partner is a message page r0 12 acknowledge 2 (ack2) 0 = link partner cannot comply with the message 1 = link partner complies with the message r0 11 toggle (t) 0 = previous value of the transmitted link code word equalled logic one 1 = previous value of the transmitted link code word equalled logic zero r0 10:0 message/ unformatted code field mp = 1: code interpreted as message page mp = 0: code interpreted as unformatted page r 0x000 1. r = read only 2. default value at the start of auto-negotiation code word transmission. table 92. port configuration register (address 16, hex 10) (sheet 1 of 2) bit name description type 1 default 15 reserved write as 0, ignore on read r/w 0 14 link disable 0 = normal operation 1 = force link pass (sets appropriate registers and leds to pass) note: setting this bit in 100 mbps mode by-passes the descrambler lock requirement to establish link and forces the link to the link-good state. setting this bit produces unreliable results if the descrambler is not locked, r/w 0 13 transmit disable 0 = normal operation 1 = disable twisted-pair transmitter r/w 0 12 bypass scramble (100base-tx) 0 = normal operation 1 = bypass scrambler and descrambler r/w 0 11 reserved write as 0, ignore on read r/w 0 10 jabber (10base-t) 0 = normal operation 1 = jabber function is enabled; however, jabber status reporting to register bit 1.1 is disabled r/w 0 1. r/w = read/write 2. lshr = default value is derived from a single device input pin state or a group of device input pin states as the pin(s) are latched at startup or hardware reset. 3. the default value of register bit 16.0 is determined by the g_fx/tp pin. if g_fx/tp is tied low, the default value of register bit 16.0 = 0. if g_fx/tp is not tied low, the default value of register bit 16.0 = 1. the bga15 package does not have a g_fx/tp hardware configuration pin. 4. the default value of register bit 16.5 is determ ined by the preasel pin. the bga15 package does not have a preasel hardware configurat ion pin and has a default of 0. 5. the bga15 package does not support fiber. default for the bga15 package is 0. 6. na means the bits do not have a default va lue and may initially contain any value.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 208 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 9 reserved write as 0, ignore on read. r/w 0 8 tp loopback (10base-t) 0 = normal operation 1 = disable twisted-pair loopback during half-duplex operation note: valid function in smii and s-smii modes only. r/w 1 7reserved write as 1, ignore on read r/w 1 6 reserved write as 0, ignore on read r/w 0 5 preamble enable 10 mbps 0 = no preamble (default) 1 = preamble enabled note: default for bga15 package is 0. r/w lshr 2,4 100 mbps no effect n/a 4 reserved write as 0, ignore on read r/w 0 3 reserved write as 0, ignore on read r/w 0 2 far end fault transmission enable 0 = disable far end fault transmission 1 = enable far end fault transmission r/w 1 invalid for bga15 write as '0', ignore on read (bga15). 1 reserved write as 0, ignore on read. r/w 0 0 fiber select 5 0 = select twisted-pair mode for this port 1 = select fiber mode for this port r/w lshr 2,3 reserved for bga15 write as '0', ignore on read (bga15). note: default for bga15 is 0. table 92. port configuration register (address 16, hex 10) (sheet 2 of 2) bit name description type 1 default 1. r/w = read/write 2. lshr = default value is derived from a single device input pin state or a gr oup of device input pin states as the pin(s) are latched at startup or hardware reset. 3. the default value of register bit 16.0 is determined by the g_fx/tp pin. if g_fx/tp is tied low, the default value of register bit 16.0 = 0. if g_fx/tp is not tied low, the default value of register bit 16.0 = 1. the bga15 package does not have a g_fx/tp hardware configuration pin. 4. the default value of register bit 16.5 is determi ned by the preasel pin. the bga15 package does not have a preasel hardware configuration pin and has a default of 0. 5. the bga15 package does not support fiber. default for the bga15 package is 0. 6. na means the bits do not have a defaul t value and may initially contain any value.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 209 document number: 249241 revision number: 007 revision date: august 28, 2003 table 93. quick status register (address 17, hex 11) (sheet 1 of 2) bit name description type 1 default 2 15 reserved write as 0, ignore on read r 0 14 10/100 mode 0 = the lxt9785/lxt9785e is operating in 10 mbps mode 1 = the lxt9785/lxt9785e is operating in 100 mbps mode note: the status is valid for tx and fx operation. r0 13 transmit status 0 = the lxt9785/lxt9785e is not transmitting a packet 1 = the lxt9785/lxt9785e is transmitting a packet r lh 0 12 receive status 0 = packet has not been received since last read 1 = packet has been received since last read r lh 0 11 collision status 0 = a collision is not occurring 1 = a collision is occurring note: this bit is set when jabber is detected, regardless of duplex. r lh 0 10 link 0 = link is down 1 = link is up r0 9 duplex mode 0 = half-duplex 1 = full-duplex r0 8 auto-negotiation 0 = the lxt9785/lxt9785e is in manual mode 1 = the lxt9785/lxt9785e is in auto-negotiation mode this signal is based upon register bit 0.12. rnote 3 7 auto-negotiation complete 0 = auto-negotiation process is not complete 1 = auto-negotiation process is complete r0 6 fifo error 0 = no fifo error occurred 1 = fifo error occurred (overflow or underflow) r lh 0 5polarity 0 = polarity is not reversed 1 = polarity is reversed note: during 100 mbps operation, this bit is not valid and may vary. auto mdix activity may increase the variability. r0 1. r = read only, lh = latching high ? cleared when read. 2. the default values are updated on completion of reset and reflect the status or change in status at that time. intel recommends that the register status be read on completion of reset. 3. the default value is determined by the default value of register bit 0.12. 4. lshr = default value is derived from a single device i nput pin state or a group of device input pin states as the pin(s) are latched at startup or hardware reset. 5. default values are set by the hardware configur ation pause pin. the bga15 package does not have a pause hardware configuration pin. the default for the bga15 package is 0.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 210 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 4 pause 0 = the lxt9785/lxt9785e is not pause capable 1 = the lxt9785/lxt9785e is pause capable note: this bit is not affected by register bit 4.10. note: the default for the bga15 package is 0. rlshr 4,5 3error 0 = no error occurred 1 = error occurred (remote fault, rxercntful, fifo error, jabber, parallel detect fault) note: the register is cleared when the registers that generated the error condition are read. r0 2:0 reserved write as 0, ignore on read. r 0 table 93. quick status register (address 17, hex 11) (sheet 2 of 2) bit name description type 1 default 2 1. r = read only, lh = latching high ? cleared when read. 2. the default values are updated on completion of reset and reflect the status or change in status at that time. intel recommends that the register status be read on completion of reset. 3. the default value is determined by t he default value of register bit 0.12. 4. lshr = default value is derived from a single device input pin state or a group of device input pin states as the pin(s) are latched at startup or hardware reset. 5. default values are set by the hardware configur ation pause pin. the bga15 package does not have a pause hardware configuration pin. the default for the bga15 package is 0.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 211 document number: 249241 revision number: 007 revision date: august 28, 2003 table 94. interrupt enable register (address 18, hex 12) bit name description type 1 default 15:14 2 rxfifo initial fill 00 = reserved 01 = low, 16 bits 10 = normal, 32 bits (default) 11 = jumbo packets, 128 bits r/w lshr 4,5 13 sfd frame alignment 3 (rxdv asserts with crs when enabled) 10 mbps when register bit 16.5 = 1, preamble is not suppressed. r/w 0 0 = disabled 1 = enabled when register bit 16.5 = 0, sfd is always aligned, and preamble is suppressed. 100 mbps 0 = disabled 1 = enabled r/w 0 when enabled, all but one byte of preamble is suppressed. 12:9 reserved write as 0, ignore on read r/w 0000 8 cntrmsk mask for counter full 0 = do not allow event to cause interrupt 1 = enable event to cause interrupt r/w 0 7anmsk mask for auto-negotiate complete 0 = do not allow event to cause interrupt 1 = enable event to cause interrupt r/w 0 6 speedmsk mask for speed interrupt 0 = do not allow event to cause interrupt 1 = enable event to cause interrupt r/w 0 5 duplexmsk mask for duplex interrupt 0 = do not allow event to cause interrupt 1 = enable event to cause interrupt r/w 0 4 linkmsk mask for link status interrupt 0 = do not allow event to cause interrupt 1 = enable event to cause interrupt r/w 0 3 isolmsk mask for isolate interrupt 0 = do not allow event to cause interrupt 1 = enable event to cause interrupt r/w 0 2 reserved write as 0, ignore on read r/w 0 1inten 0 = disable interrupts on this port 1 = enable interrupts on this port r/w 0 0tint 0 = normal operation 1 = test force interrupt on mdint r/w 0 1. r/w = read/write 2. in 10 mbps operation, register bit 18.13 = 1 cannot be used when register bits 18.15:14 = ?11? and in rmii mode, registers bits 18.15:14 = ?11? or ?10? cannot be used because the minimum inter gap packet becomes less than specified in the *ieee 802.3 specification. 3. sfd frame alignment is applicable to smii and ss-smii only. 4. lshr = default value is derived from a single device input pin state or a group of device input pin states as the pin(s) are latched at startup or hardware reset 5. default values are set by hardware conf iguration pins fifosel1 and fifosel0 (see table 17, ?intel? lxt9785/lxt9785e receive fifo depth considerations? on page 50 ).
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 212 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 table 95. interrupt status register (address 19, hex 13) bit name description type 1 default 2 15:9 reserved write as 0, ignore on read r 0 8rxercntful rxer counter full status. 0 = the internal counters have not reached maximum values 1 = one of the internal counters has reached its maximum value r/lh 0 7andone auto-negotiation status. 0 = auto-negotiation has not completed 1 = auto-negotiation has completed r/lh n/a 6 speedchg speed change status. 0 = a speed change has not occurred since last reading this register 1 = a speed change has occurred since last reading this register r/lh 0 5 duplexchg duplex change status. 0 = a duplex change has not occurred since last reading this register 1 = a duplex change has occurred since last reading this register r/lh 0 4 linkchg link status change status. 0 = a link change has not occurred since last reading this register 1 = a link change has occurred since last reading this register r/lh 0 3 isolate mii isolate change status. 0 = an isolate change has not occurred since last reading this register 1 = an isolate change has occurred since last reading this register r/lh 0 2mdint 0 = interrupt not pending 1 = interrupt pending r/lh 0 1:0 reserved reserved r 0 1. r = read only, lh = latching high ? cleared when read 2. the default values are updated on completion of reset and reflect the status or change in status at that time. intel recommends that the register status be read on completion of reset.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 213 document number: 249241 revision number: 007 revision date: august 28, 2003 table 96. led configuration register (address 20, hex 14) (sheet 1 of 2) bit name description type 1 default 15:12 led1 programming bits 0000 = display speed status (continuous, default) 0001 = display transmit status (stretched) 0010 = display receive status (stretched) 0011 = display collision status (stretched) 0100 = display link status (continuous) 0101 = display duplex status (continuous) 0110 = display isolate status (continuous) 0111= display receive or transmit activity (stretched) 1000= est mode- turn led on (continuous) 1001= test mode- turn led off (continuous) 1010= test mode- blink led fast (continuous) 1011= test mode- blink led slow (continuous) 1100= display link and receive status combined 2 (stretched) 3 1101= display link and activity status combined 2 (stretched) 3 1110= display duplex and collision status combined 4 (stretched) 3 1111 = display link and rxer status combined 2 (blink) r/w 0000 11:8 led2 programming bits 0000 = display speed status 0001 = display transmit status 0010 = display receive status 0011 = display collision status 0100 = display link status 0101 = display duplex status 0110 = display isolate status 0111= display receive or transmit activity 1000= test mode- turn led on 1001= test mode- turn led off 1010= test mode- blink led fast 1011= test mode- blink led slow 1100= display link and receive status combined 2 (stretched) 3 1101= display link and activity status combined 2 (default) (stretched) 3 1110= display duplex and collision status combined 4 (stretched) 3 1111= display link and rxer status combined 2 (blink) r/w 1101 1. r/w = read/write 2. link status is the primary led driver. the led is asserted (solid on ) when the link is up. the secondary led driver (receive, activity, or error) causes the led to change state (blink). 3. combined event led settings are not affected by puls e stretch register bit 20.1. these display settings are stretched regardless of the value of 20.1. 4. duplex status is the primary led driver. the led is asserted (solid on) w hen the link is full-duplex. collision status is the secondary led driver. the led changes state (blinks) when a collision occurs.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 214 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 7:4 led3 programming bits 0000 = display speed status 0001 = display transmit status 0010 = display receive status 0011 = display collision status 0100 = display link status 0101 = display duplex status 0110 = display isolate status 0111= display receive or transmit activity 1000= test mode- turn led on 1001= test mode- turn led off 1010= test mode- blink led fast 1011= test mode- blink led slow 1100= display link and receive status combined 2 (stretched) 3 1101= display link and activity status combined 2 (stretched) 3 1110= display duplex and collision status combined 4 (default) (blink) 3 1111 = display link and rxer status combined 2 (blink) r/w 1110 reserved for bga15 write as '1001', ignore on read (bga15) 3:2 ledfreq 00 = stretch led events to 30 ms 01 = stretch led events to 60 ms 10 = stretch led events to 100 ms 11 = reserved r/w 00 1 pulse- stretch 0 = disable pulse stretching of all leds 3 1 = enable pulse stretching of all leds note: receive activity leds are initially active based upon carrier sense. r/w 1 0 reserved write as 0, ignore on read r/w 0 table 97. receive error count register (address 21, hex 15) bit name description type 1 default 15:0 receive error count a 16-bit counter value indicating the number of times a receive packet with errors occurred. only one event gets counted per packet. when maximum count is reached, the 16-bit counter remains full until cleared. r/ lh 0x0000 1. r = read only, lh = latching high ? cleared when read note: intel recommends reading this register once every time link is es tablished to clear the register. table 96. led configuration register (address 20, hex 14) (sheet 2 of 2) bit name description type 1 default 1. r/w = read/write 2. link status is the primary led driver. the le d is asserted (solid on) when the link is up. the secondary led driver (receive , activity, or error) causes the led to change state (blink). 3. combined event led settings are not affected by puls e stretch register bit 20.1. these display settings are stretched regardless of the value of 20.1. 4. duplex status is the primary led driver. the led is asserted (solid on) when the link is full-duplex. collision status is the secondary le d driver. the led changes state (blinks) when a collision occurs.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 215 document number: 249241 revision number: 007 revision date: august 28, 2003 table 98. rmii out-of-band signaling register (address 25, hex 19) bit name description type 1 default bga15 15:0 reserved for bga15 write as 0, ignore on read. r/w 0x0000 pqfp and bga23 15:7 reserved write as 0, ignore on read r/w 0x000 6:4 bit1 these three bits select which status information is available on the rxdata(1) bit of the rmii bus. 000 = link 001 = speed 010 = duplex 011 = auto-negotiation complete 100 = polarity reversed 101 = jabber detected 110 = interrupt pending 111 = reserved r/w 000 3:1 bit0 these three bits select which status information is available on the rxdata(0) bit of the rmii bus. 000 = link 001 = speed 010 = duplex 011 = auto-negotiation complete 100 = polarity reversed 101 = jabber detected 110 = interrupt pending 111 = reserved r/w 000 0 progrmii 0 = disable out-of-band signaling. 1 = enable programmable rmii out-of-band signaling. when enabled, register bits 6:1 specify which status bits are available on the rmii rxdata data bus. note: out-of-band signaling is disabled when the isolate mode is enabled by setting register bit 0.10. r/w 0 1. r/w = read/write note: the bga15 package does not support rmii operation.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 216 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 table 99. trim enable register (address 27, hex 1b) (sheet 1 of 2) bit name description type 5 default 15:13 reserved write as 0, ignore on read r n/a 12 reserved write as 0, ignore on read. r/w 0 11:10 per-port rise time control 00 = 3.3 ns 01 = 3.6 ns 10 = 3.9 ns 11 = 4.2 ns note: values represent nom inal load conditions. r/w lshr 1,2 9amdix_en 0 = disable auto mdi/mdix 1 = enable auto mdi/mdix r/w lshr 1,3 8mdix 0 = mdi, transmit on pair a (tpfin n /tpfip n ) and receive on pair b (tpfon n /tpfop n ) 1 = mdix transmit on pair b (tpfon n /tpfop n ) and receive on pair a (tpfin n /tpfip n ) note: manual mdi/mdix selection (this bit is ignored when register bit 27.9 = 1). note: bga15 does not support the mdix hardware configuration. r/w lshr 1,4 7 analog loopback 0 = disable analog loopback 1 = enable analog loopback (twist ed-pair transmit outputs are active) note: in fiber mode, sd for the port must be asserted. r/w 0 6 dis_en dte discovery process enable. 0 = disable dte discovery process 1 = enable dte discovery process restart auto-negotiation after writing to this bit to ensure proper operation. r/w 0 5 reserved write as 0, ignore on read. r/w 0 4 power_en power enable (requires auto-negotiation enable register bit 0.12 = 1). 0 = remote-power dte not discovered; process may not be complete. 1 = potential remote-power dte discovered; indication to turn on power over the cable. r0 1. lshr = default value is derived from a single device i nput pin state or a group of device input pin states as the pin(s) are latched at startup or hardware reset. 2. default values for register bits 27.11:10 are determined by the txslew pins. 3. default value for register bit 27.9 is determined by the amdix_en pin. 4. default value for register bit 27.8 is determined by the mdix pin. bga15 does not support the mdix hardware configuration. the bga15 default = 0. 5. r/w = read/write, r = read only, lh = latching high ? cleared when read. 6.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 217 document number: 249241 revision number: 007 revision date: august 28, 2003 3 slp_det standard link partner detected. 0 = standard link partner not discovered; process may not be complete. 1 = standard link partner discov ered; indication not to turn on power over the cable. note: this bit is only valid while link is down. r, lh 0 2 lfit expired link fail inhibit timer expiration indicator. valid only when slp_det = 1. 0 = link fail inhibit timer has not expired or standard link partner not discovered 1 = link fail inhibit timer expi red with a standard link partner detected since last register read or link establishment r, lh 0 1:0 reserved write as 0, ignore on read. r 00 table 99. trim enable register (address 27, hex 1b) (sheet 2 of 2) bit name description type 5 default 1. lshr = default value is derived from a single device input pin state or a group of device input pin states as the pin(s) are latched at startup or hardware reset. 2. default values for register bits 27.11 :10 are determined by the txslew pins. 3. default value for register bit 27.9 is determined by the amdix_en pin. 4. default value for register bit 27.8 is determined by the mdix pin. bga15 does not support the mdix hardware configuration. the bga15 default = 0. 5. r/w = read/write, r = read only, lh = latching high ? cleared when read. 6. table 100. cable diagnostics register (address 29, hex 1d) (sheet 1 of 2) bit name description type 1 default 2 15:14 reserved write as 01, ignore on read r/w 01 13:11 start-test 000 = do not perform cable fault test (default) 101 = perform long cable fault test only 110 = perform short cable fault test only once register bit 29.9 is set, the start-test bits will clear when read. any other combination of the register bit settings are reserved and should not be used. r/w lh 000 10 cd_en 0 = normal operation 1 = enable cable diagnostic tests. forces link to drop. r/w 0 1. r/w = read/write, r = read only, lh = latching high, cleared when read 2. recommended default value.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 218 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 9 test_done 0 = testing is still in progress 1 = testing is complete the line fault counter and fault_type bits are valid. r lh 0 8 fault_type 0 = open condition has been detected 1 = short condition has been detected r lh 0 7:0 line fault counter ?ff? if no line fault is found, or distance to fault, approximately 1 m * counter value (refer to section 4.13, ?cable diagnostics overview? on page 160 for details). (valid only when test_done bit is set.) r lh 0x00 table 100. cable diagnostics register (address 29, hex 1d) (sheet 2 of 2) bit name description type 1 default 2 1. r/w = read/write, r = read only, lh = latching high, cleared when read 2. recommended default value.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 219 document number: 249241 revision number: 007 revision date: august 28, 2003 table 101. intel ? lxt9785/lxt9785e register bit map (sheet 1 of 2) reg title bit fields addr b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 control register (address 0) control reset loopback speed select a/n enable power down isolate re-start a/n duplex mode col test speed select reserved 0 status register (address 1) status 100base-t4 100base- x full- duplex 100base-x half-duplex 10 mbps full- duplex 10 mbps half- duplex 100base- t2 full- duplex 100base-t2 half-duplex extended status reserved mf preamble suppress a/n complete remote fault a/n ability link status jabber detect extended capability 1 phy id registers (address 2 and 3) phy id 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 2 phy id2 phy id no mfr model no mfr rev no model va r i a n t 3 auto-negotiation advertisement register (address 4) a/n advertise next page reserved remote fault reserved asymm pause pause 100base-t4 100base- tx full- duplex 100base- tx 10base-t full-duplex 10base-t ieee selector field 4 auto-negotiation link partner base page ability register (address 5) a/n link ability next page ack remote fault reserved asymm pause pause 100base-t4 100base- tx full- duplex 100base- tx 10base-t full-duplex 10base-t ieee selector field 5 auto-negotiation expansion register (address 6) a/n expansion reserved base page parallel detect fault link partner next page able next page able page received link partner a/n able 6 auto-negotiation next page transmit register (address 7) a/n next page txmit next page reserved message page ack 2 toggle message / unformatted code field 7 auto-negotiation link partner next page ability register (address 8) a/n link next page next page ack message page ack 2 toggle message / unformatted code field 8 port configuration register (address 16)
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 220 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 port config reserved link disable txmit disable bypass scrambler (100base- tx) bypass 4b/5b (100base -tx) jabber (10t) sqe (10t) tp loopback (10t) reserved reserved pre_en reserved reserved far end fault enable reserved fiber select 16 quick status register (address 17) quick status reserved 10/100 mode transmit status receiver status collision status link duplex mode auto-neg auto-neg complete fifo error polarity pause error reserved reserved reserved 17 interrupt enable register (address 18) interrupt enable reserved counter mask auto-neg mask speed mask duplex mask link mask isolate mask reserved interrupt enable test interrupt 18 interrupt status register (address 19) interrupt status reserved rxer counter full auto-neg done speed change duplex change link change isolate change md interrupt reserved reserved 19 led configuration register (address 20) led config led1 led2 led3 led freq pulse stretch reserved 20 receive error count register (address 21) rcv error count receive error count 21 programmable rmii out-of-band signaling register (register 25) rmii oob signaling reserved bit 1 bit 0 program rmii 25 trim enable register (address 27) trim enable reserved per port rise time control amdix_en mdix analog loopback dis_en loop back speed up enable power_en slp_det lfit expired reserved 27 cable diagnostics register (address 29) cable diagnostics reserved start-test cd_en test-done fault_ type line fault counter 29 table 101. intel ? lxt9785/lxt9785e register bit map (sheet 2 of 2) reg title bit fields addr b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 221 document number: 249241 revision number: 007 revision date: august 28, 2003 8.0 package specifications figure 64. intel ? lxt9785/lxt9785e 208-pin pqfp plastic package specification e / 2 a 1 a 2 l a b l 1 3 2 d d 1 e e 1 e dim millimeters min max a - 4.10 a1 0.25 - a2 3.20 3.60 b 0.17 0.27 d 30.30 30.90 d 1 27.70 28.30 e 30.30 30.90 e 1 27.70 28.30 e .50 basic l 0.50 0.75 l 1 1.30 ref q 0 7 2 5 16 3 5 16 208-pin plastic quad flat package ? part number lxt9785hc, lxt9785ehc, lxt9785he ? commercial temperature range (0 c to 70 c) ? extended temperature range (-40 c to +85 c)
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 222 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 figure 65. intel ? lxt9785/lxt9785e 241-ball bga23 package specs - top/side view (lxt9785bc) pin a1 i.d. pin a1 corner d d1 e e1 top view a a2 a1 c side view 241_pkg1.vsd 14.70 ref 14.70 ref 45 chamfer (4 places) 30 seating plane
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 223 document number: 249241 revision number: 007 revision date: august 28, 2003 figure 66. intel ? lxt9785/lxt9785e 241-ball bga23 package specs - bottom view (lxt9785bc) pin a1 corner b e 2 10 16 3 5 7 9 11 13 15 17 1 4 6 8 12 14 a b c d e f g h j k l m n p r t u 241 bga bottom view j l e
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 224 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 intel ? lxt9785/lxt9785e 241-ball bga23 package dimensions symbol min nominal max units note a 2.19 2.38 2.57 mm a1 0.50 0.60 0.70 mm a2 1.12 1.17 1.22 mm d 22.90 23.00 23.10 mm d1 19.30 19.50 19.70 mm e 22.90 23.00 23.10 mm e1 19.30 19.50 19.70 mm e 1.27 (solder ball pitch) mm i 1.34 ref. mm j 1.34 ref. mm m 17 x 17 matrix mm b 0.60 0.75 0.90 mm c 0.52 0.56 0.60 mm e 1.27 mm all dimensions and tolerances conform to ansi y14.5- 1982. dimension is measur ed at maximum solder ball diameter parallel to primary datum (-c-). primary dat um (-c-) and seating plane are defined by the spherical crowns of the solder balls.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 225 document number: 249241 revision number: 007 revision date: august 28, 2003 figure 67. intel ? lxt9785mbc 196-ball bga15 package specs - top/side view (lxt9785mbc)
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 226 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 table 102. intel? lxt9785mbc 196-ball bga15 package dimensions symbol min nominal max units note a 1.62 1.81 2.00 mm a1 0.30 0.40 0.50 mm a2 0.80 0.85 0.90 mm d 14.90 15.00 15.10 mm d1 12.80 13.00 13.20 mm e 14.90 15.00 15.10 mm e1 12.80 13.00 13.20 mm e 1.00 (solder ball pitch) mm i1.00 ref. mm j1.00 ref. mm m 14 x 14 matrix mm b 0.40 0.50 0.60 mm c 0.52 0.56 0.60 mm e 1.00 mm note: all dimensions and tolerances conform to ansi y14.5-1982.dimension is measured at maximum solder ball diameter parallel to primary datum (-c-). primary datum (-c-) and seating plane are defined by the spherical crowns of the solder balls.
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers datasheet 227 document number: 249241 revision number: 007 revision date: august 28, 2003 9.0 ordering information table 103. product information number revision qualification tray mm tape & reel mm hblxt9785hc.d0 853353 d0 s 853353 tray hblxt9785hc.d0 853355 d0 s 853355 tape & reel fwlxt9785bc.d0 853308 d0 s 853308 tray fwlxt9785bc.d0 853312 d0 s 853312 tape & reel hblxt9785ehc.d0 853334 d0 s 853334 tray hblxt9785ehc.d0 853335 d0 s 853335 tape & reel fwlxt9785ebc.d0 853300 d0 s 853300 tray fwlxt9785ebc.d0 853304 d0 s 853304 tape & reel hblxt9785he.d0 853357 d0 s 853357 tray hblxt9785he.d0 853363 d0 s 853363 tape & reel gdlxt9785mbc.d0 d0 q tbd tbd gdlxt9785mbc.d0 d0 q tbd tbd
lxt9785 and lxt9785e advanced 8-port 10/100 mbps phy transceivers 228 datasheet document number: 249241 revision number: 007 revision date: august 28, 2003 figure 68. ordering information - sample temperature range a c e = ambient (0 - 55 c) = commercial (0 - 70 c) = extended (-40 - +85 c) product revision xn = 2 alphanumeric characters build format e000 e001 = tray = tape and reel fw s d0 c b 9785 lxt e001 internal package designator l p n q h t b c e k = lqfp = plcc = dip = pqfp = qfp with heat spreader = tqfp = bga = cbga = tbga = hsbga (bga with heat slug) qualification q s = pre-production material = production material ixa product prefix lxt ixe ixf ixp = phy layer device = switching engine = formatting device (mac) = network processor intel package designator dj fa fl fw hb hd hf hg s gc n = lqfp = tqfp = pbga (<1.0 mm pitch) = pbga (1.27 mm pitch) = qfp with heat spreader = qfp with heat slug = cbga = soic = qfp = tbga = plcc xxxx = 3-5 digit alphanumeric product code

▲Up To Search▲

Price & Availability of DJIXFECD0SE000

	To Download DJIXFECD0SE000 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .